US5236859A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making stacked-capacitor for a dram cell same
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-12-10
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Granted: 1993-08-17
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Expires: 2011-12-10
Abstract
Abstract There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.
Inventors
- 👤 Dong-Joo Bae
- 👤 Won-Shik Baek
- 👤 Kyu-Hyun Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:00
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
212 words
A process for manufacturing a stacked capacitor of a DRAM cell on a semiconductor substrate where an element separating oxide film, a source region and a drain region are formed, comprising the steps of: coating said semiconductor substrate with a layer insulating film, a nitrified film and a first oxide film after a bit line is formed thereon; forming a contact opening which exposes the surface of said source region by etching in consecutive order the first oxide film, nitrified film and layer insulating film on said source region; depositing a first polysilicon layer on the whole surface of the substrate; coating the surface of said polysilicon layer with a second oxide film to an extent that said contact opening is filled, and selectively etching said oxide film in a remaining portion excluding an upside of said contact opening; depositing a second polysilicon layer on the whole surface of said substrate; selectively etching the first and second polysilicon layers in a remaining portion excluding a portion where said first polysilicon layer contacts with said second polysilicon layer; removing said first and second oxide films; forming a dielectric film on the exposed surfaces of said first and second polysilicon layers; and forming a third polysilicon layer on the surface of said dielectric film.
Claim 2
Dependent Claim
212 words
A process for manufacturing a stacked capacitor of a DRAM cell on a semiconductor substrate where an element separating oxide film, a source region and a drain region are formed, comprising the steps of: coating said semiconductor substrate with a layer insulating film, a nitrified film and a first oxide film after a bit line is formed thereon; forming a contact opening which exposes the surface of said source region by etching in consecutive order the first oxide film, nitrified film and layer insulating film on said source region; depositing a first polysilicon layer on the whole surface of the substrate; coating the surface of said polysilicon layer with a second oxide film to an extent that said contact opening is filled, and selectively etching said oxide film in a remaining portion excluding an upside of said contact opening; depositing a second polysilicon layer on the whole surface of said substrate; selectively etching the first and second polysilicon layers in a remaining portion excluding a portion where said first polysilicon layer contacts with said second polysilicon layer; removing said first and second oxide films; forming a dielectric film on the exposed surfaces of said first and second polysilicon layers; and forming a third polysilicon layer on the surface of said dielectric film.
Claim 3
Dependent Claim
41 words
A method according to claim 1, wherein said first polysilicon layer contacts with said second polysilicon layer in the portion adjacent to both ends of said second oxide film in said step of selectively etching the first and second polysilicon layers.
Claim 4
Dependent Claim
21 words
A method according to claim 1, wherein said first and second polysilicon layers serve as a storage electrode of the capacitor.
Claim 5
Dependent Claim
19 words
A method according to claim 1, wherein said third polysilicon layer serves as a plate electrode of the capacitor.
Claim 6
Dependent Claim
21 words
A method according to claim 2, wherein said first and second polysilicon layers serve as a storage electrode of the capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-08-16 | 1997-02-15 | 1997-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-16 | 2001-02-15 | 2001-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-16 | 2005-02-15 | 2005-08-17 | $7700.00 | Window Closed / Lapsed |