Method for fabricating a semiconductor memory cell

Claim 1

A method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor patterned simultaneously with a polysilicon pad and a polysilicon storage node by a self-alignment method without a mask, comprising the successive steps of: (a) forming a field oxide layer and a gate on a substrate; (b) forming thereon a CVD silicon oxide layer and successive deposition layers of a silicon nitride pad and a silicon oxide pad layer; (c) patterning said silicon oxide pad layer and then patterning the said silicon nitride pad layer and said CVD silicon oxide layer successively to form a buried contact; (d) forming thereon and patterning a first polysilicon layer and a CVD oxide for planarization; (e) forming thereon, in order, a second polysilicon layer and a silicon oxide layer; (f) etching said silicon oxide layer by using an anisotropic dry etching method in order to form a silicon oxide sidewall and then etching said first and second polysilicon layers; (g) removing the silicon oxide sidewall, the CVD oxide for planarization and the silicon nitride pad layer by a wet etching method; (h) forming a dielectric film; (i) forming a third polysilicon layer and patterning to form a cell plate; and (j) forming an insulated layer and etching it to form a contact and a bit line.

Claim 2

A method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor patterned simultaneously with a polysilicon pad and a polysilicon storage node by a self-alignment method without a mask, comprising the successive steps of: (a) forming a field oxide layer and a gate on a substrate; (b) forming thereon a CVD silicon oxide layer and successive deposition layers of a silicon nitride pad and a silicon oxide pad layer; (c) patterning said silicon oxide pad layer and then patterning the said silicon nitride pad layer and said CVD silicon oxide layer successively to form a buried contact; (d) forming thereon and patterning a first polysilicon layer and a CVD oxide for planarization; (e) forming thereon, in order, a second polysilicon layer and a silicon oxide layer; (f) etching said silicon oxide layer by using an anisotropic dry etching method in order to form a silicon oxide sidewall and then etching said first and second polysilicon layers; (g) removing the silicon oxide sidewall, the CVD oxide for planarization and the silicon nitride pad layer by a wet etching method; (h) forming a dielectric film; (i) forming a third polysilicon layer and patterning to form a cell plate; and (j) forming an insulated layer and etching it to form a contact and a bit line.

Claim 5

A method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor patterned simultaneously with a polysilicon pad and a polysilicon storage node by a self-alignment method without a mask, comprising the successive steps of: (a) forming a field oxide (42) and a gate on a substrate (41); (b) depositing and patterning thereon a first silicon oxide layer (44); (c) forming and patterning a first doped polysilicon layer (45), so that only a bit line (46) portion thereof remains; (d) patterning a bit line (46), and a second silicon oxide layer (47) and again forming thereon a subsequent silicon oxide layer and forming a side wall (48) by etching said subsequent silicon oxide layer; (e) forming thereon, in order a second polysilicon layer (49), a third silicon oxide layer (50), and a silicon nitride layer (51); (f) patterning said third silicon oxide layer (50) and said silicon nitride layer (51), and forming and patterning a doped third polysilicon layer (52) by an anisotropic dry etching method, so that the doped third polysilicon layer (52) remains only in a side thereof; (g) removing said silicon nitride layer (51) by a wet-etching method, and forming and patterning a doped fourth polysilicon layer (53) by a isotropic dry etching method to form a top of a polysilicon storage node in a shape of a peak; and (h) removing said third silicon oxide (50) layer by a wet etching method, and forming a dielectric film (54) and a cell plate.

Claim 6

A method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor patterned simultaneously with a polysilicon pad and a polysilicon storage node by a self-alignment method without a mask, comprising the successive steps of: (a) forming a field oxide (42) and a gate on a substrate (41); (b) depositing and patterning thereon a first silicon oxide layer (44); (c) forming and patterning a first doped polysilicon layer (45), so that only a bit line (46) portion thereof remains; (d) patterning a bit line (46), and a second silicon oxide layer (47) and again forming thereon a subsequent silicon oxide layer and forming a side wall (48) by etching said subsequent silicon oxide layer; (e) forming thereon, in order a second polysilicon layer (49), a third silicon oxide layer (50), and a silicon nitride layer (51); (f) patterning said third silicon oxide layer (50) and said silicon nitride layer (51), and forming and patterning a doped third polysilicon layer (52) by an anisotropic dry etching method, so that the doped third polysilicon layer (52) remains only in a side thereof; (g) removing said silicon nitride layer (51) by a wet-etching method, and forming and patterning a doped fourth polysilicon layer (53) by a isotropic dry etching method to form a top of a polysilicon storage node in a shape of a peak; and (h) removing said third silicon oxide (50) layer by a wet etching method, and forming a dielectric film (54) and a cell plate.