Method of processing a semiconductor wafer using a contact etch stop

Claim 1

A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining at least one high elevation conductive region and at least one low elevation conductive region; providing a planarized insulating dielectric layer atop the wafer; patterning the insulating dielectric layer for defining a plurality of contact openings through the insulating dielectric to selected conductive regions at the varying elevations; first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made; after first etching, selectively depositing a layer of an etch stop material to a thickness atop the outer surface of the high elevation conductive region; and second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching.

Claim 2

A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining at least one high elevation conductive region and at least one low elevation conductive region; providing a planarized insulating dielectric layer atop the wafer; patterning the insulating dielectric layer for defining a plurality of contact openings through the insulating dielectric to selected conductive regions at the varying elevations; first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made; after first etching, selectively depositing a layer of an etch stop material to a thickness atop the outer surface of the high elevation conductive region; and second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching.

Claim 12

A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining at least one high elevation conductive region and at least one low elevation conductive region; providing a planarized insulating dielectric layer atop the wafer; providing a layer of photoresist atop the planarized insulating dielectric layer; photo exposing and developing the photoresist to define a pattern of a plurality of selected openings through the photoresist to the insulating dielectric layer for definition of a plurality of contact openings through the insulating dielectric layer to conductive regions at the varying elevations; first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made; after first etching and with the photoresist layer still in place, selectively depositing a layer of an etch stop material to a thickness atop the outer surface of the high elevation conductive region; with the photoresist layer still in place, second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching; and removing photoresist from the wafer.

Claim 13

A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining at least one high elevation conductive region and at least one low elevation conductive region; providing a planarized insulating dielectric layer atop the wafer; providing a layer of photoresist atop the planarized insulating dielectric layer; photo exposing and developing the photoresist to define a pattern of a plurality of selected openings through the photoresist to the insulating dielectric layer for definition of a plurality of contact openings through the insulating dielectric layer to conductive regions at the varying elevations; first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made; after first etching and with the photoresist layer still in place, selectively depositing a layer of an etch stop material to a thickness atop the outer surface of the high elevation conductive region; with the photoresist layer still in place, second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching; and removing photoresist from the wafer.

Claim 23

A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining, a) a high elevation conductive region, b) a next highest elevation conductive region below the high elevation conductive region, and c) a low elevation conductive region; providing a planarized insulating dielectric layer atop the wafer, the planarized insulating dielectric layer having an upper surface, the upper surface being elevationally separated from the outer surface of the next highest conductive region by a first distance; providing a layer of photoresist atop the planarized insulating dielectric layer; photo exposing and developing the photoresist to define a pattern of a plurality of selected openings through the photoresist to the insulating dielectric layer upper surface for definition of a plurality of contact openings through the insulating dielectric layer to conductive regions at the varying elevations; first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made and thereby defining contact opening first bases, the first etching leaving a second distance between the first bases and the outer surface of the low elevation conductive region, the first distance being greater than the second distance; after first etching, selectively depositing a layer of an etch stop material to a thickness atop the outer surface of the high elevation conductive region; after the first etching, removing all photoresist from the wafer; and with photoresist removed from wafer, second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching.

Claim 24

A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining, a) a high elevation conductive region, b) a next highest elevation conductive region below the high elevation conductive region, and c) a low elevation conductive region; providing a planarized insulating dielectric layer atop the wafer, the planarized insulating dielectric layer having an upper surface, the upper surface being elevationally separated from the outer surface of the next highest conductive region by a first distance; providing a layer of photoresist atop the planarized insulating dielectric layer; photo exposing and developing the photoresist to define a pattern of a plurality of selected openings through the photoresist to the insulating dielectric layer upper surface for definition of a plurality of contact openings through the insulating dielectric layer to conductive regions at the varying elevations; first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made and thereby defining contact opening first bases, the first etching leaving a second distance between the first bases and the outer surface of the low elevation conductive region, the first distance being greater than the second distance; after first etching, selectively depositing a layer of an etch stop material to a thickness atop the outer surface of the high elevation conductive region; after the first etching, removing all photoresist from the wafer; and with photoresist removed from wafer, second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching.