DRAM stacked capacitor fabrication process

Claim 1

A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: a) creating a plurality of separately isolated active areas arranged in parallel rows and parallel columns; b) creating a gate dielectric layer on top of each active area; c) depositing a first conductive layer superjacent surface of said array; d) depositing a first dielectric layer superjacent said first conductive layer; e) masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over an inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer; f) creating a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; g) depositing a second dielectric layer superjacent said array surface; h) creating a first aligned buried contact location at each said digit line junction in each said active area; i) depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; j) depositing a third dielectric layer superjacent to said second conductive layer; k) masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digital lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-shaped topology; l) depositing a fourth dielectric layer superjacent said array surface; m) masking and etching a second aligned buried contact location allowing access to an active area and thereby forming vertical sidewalls within opening of said buried contact location; n) depositing a third conductive layer superjacent said fourth dielectric layer and said second buried contact opening; o) patterning said third conductive layer to form storage node plates having a v-shaped cross-section, said storage node plates conforming to said 3-dimensional, waveform shaped topology and thereby making contact to said active area at said second buried contact location; p) depositing a fifth dielectric layer on said storage node plates and etching said fifth dielectric layer to leave to leave a remnant dielectric between the storage node plates of neighboring cells thereby isolating adjacent storage node plates; q) placing a cell dielectric layer superjacent an exposed upper portion of said storage node plate, said cell dielectric layer conforming to existing waveform shaped topology, said cell dielectric layer is a layer of high dielectric constant material; and r) depositing a fourth conductive layer superjacent said cell dielectric layer, thereby forming a top cell plate common to the entire memory array.