US5700708A
Expired / Lapsed
US
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Process for fabricating storage capacitor for DRAM memory cell
Assignee: United Microelectronics Corp
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Filing: 1996-06-18
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Granted: 1997-12-23
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Expires: 2016-06-18
Abstract
Abstract A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer. The second polysilicon layer thus provides the first electrode of the storage capacitor. A dielectric layer is formed on the second polysilicon layer to provide the dielectric of the storage capacitor and a third polysilicon layer is formed on the dielectric layer to provide the second electrode of the storage capacitor.
Inventors
- 👤 Hwi-Huang Chen
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:14
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
212 words
A process for fabricating a storage capacitor for a memory cell unit of a dynamic random access memory semiconductor device, comprising the steps of: (a) forming a transistor, including a gate and a drain/source region on a silicon substrate, the gate including a first polysilicon layer covered by an insulating layer; (b) forming a silicon nitride layer directly on and covering the transistor; (c) forming a silicon oxide layer on the silicon nitride layer; (d) forming a contact opening in the silicon oxide layer and the silicon nitride layer to expose a surface of the drain/source region, wherein the silicon oxide layer has an edge portion that extends toward a cavity of the contact opening more than an edge portion of the silicon nitride layer extends toward the cavity; (e) forming a second polysilicon layer in the contact opening and covering the exposed drain region and the edge portions of the silicon oxide and silicon nitride layers, the second polysilicon layer forming a first electrode of the storage capacitor; (f) forming a dielectric layer on the second polysilicon layer, the dielectric layer forming the dielectric of the storage capacitor; and (g) forming a third polysilicon layer on the dielectric layer, the third polysilicon layer forming a second electrode of the storage capacitor.
Claim 2
Dependent Claim
212 words
A process for fabricating a storage capacitor for a memory cell unit of a dynamic random access memory semiconductor device, comprising the steps of: (a) forming a transistor, including a gate and a drain/source region on a silicon substrate, the gate including a first polysilicon layer covered by an insulating layer; (b) forming a silicon nitride layer directly on and covering the transistor; (c) forming a silicon oxide layer on the silicon nitride layer; (d) forming a contact opening in the silicon oxide layer and the silicon nitride layer to expose a surface of the drain/source region, wherein the silicon oxide layer has an edge portion that extends toward a cavity of the contact opening more than an edge portion of the silicon nitride layer extends toward the cavity; (e) forming a second polysilicon layer in the contact opening and covering the exposed drain region and the edge portions of the silicon oxide and silicon nitride layers, the second polysilicon layer forming a first electrode of the storage capacitor; (f) forming a dielectric layer on the second polysilicon layer, the dielectric layer forming the dielectric of the storage capacitor; and (g) forming a third polysilicon layer on the dielectric layer, the third polysilicon layer forming a second electrode of the storage capacitor.
Claim 3
Dependent Claim
21 words
The process of claim 1, wherein the silicon oxide layer formed in step (c) has a thickness of about 500-2,000 Å.
Claim 4
Dependent Claim
27 words
The process of claim 1, wherein the contact opening formed in step (d) is formed using a selective etching process by etching into the silicon oxide layer.
Claim 5
Dependent Claim
18 words
The process of claim 3, wherein the selective etching into the silicon oxide layer is conducted utilizing HF.
Claim 6
Dependent Claim
21 words
The process of claim 3, wherein the selective etching into the silicon oxide layer is conducted utilizing a buffered oxide etchant.
Claim 7
Dependent Claim
19 words
The process of claim 3, wherein the selective etching into the silicon oxide layer is utilizing dry etch method.
Claim 8
Dependent Claim
26 words
The process of claim 1, wherein the formation of a contact opening in step (d) comprises the step of selectively etching into the silicon nitride layer.
Claim 9
Dependent Claim
14 words
The process of claim 7, wherein said selective etching is conducted utilizing phosphoric acid.
Claim 10
Dependent Claim
17 words
The process of claim 1, wherein the second polysilicon layer has a thickness of about 1,000-5,000 Å.
Claim 11
Dependent Claim
15 words
The process of claim 1, wherein the dielectric layer includes a configuration of oxide/nitride layers.
Claim 12
Dependent Claim
15 words
The process of claim 1, wherein the dielectric layer includes a configuration of oxide/nitride/oxide layers.
Claim 13
Dependent Claim
23 words
The process of claim 1, further including the step of removing the silicon oxide and silicon nitride layers, prior to said step (f).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |