Method of increasing the surface area of a mini-stacked capacitor

Claim 1

A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: a) forming a first dielectric layer on existing surface of said silicon substrate; b) forming a second dielectric layer adjacent and coextensive said first dielectric layer; c) forming a third dielectric layer adjacent and coextensive said second dielectric layer; d) placing and patterning a masking layer to provide a storage node location opening, said opening thereby exposing a portion of said third dielectric between two adjacent digit lines; e) etching said exposed portion of third dielectric through said opening thereby exposing the underlying second dielectric; f) removing said masking layer thereby exposing the remaining third dielectric layer; g) forming a fourth dielectric layer superjacent and coextensive said remaining third dielectric layer and said exposed portion of said second dielectric; h) forming a fifth dielectric layer superjacent and coextensive said fourth dielectric layer; i) placing and patterning a second masking layer at said storage node location opening, said opening thereby exposing a portion of said fifth dielectric between two adjacent digit lines; j) etching said exposed portion of said fifth dielectric through said opening thereby exposing the underlying fourth dielectric; k) etching fourth, second and first dielectrics through said opening thereby exposing said active areas; l) removing said masking thereby exposing the remaining third dielectric layer; m) placing a conformal first conductive layer adjacent and coextensive said exposed active areas, said remaining exposed fifth dielectric and the patterned edges of said first, second, third and fourth dielectrics, said first conductive layer making physical contact to said active areas; n) masking and etching said first conductive layer thereby forming a storage node plate; o) etching said remaining fifth dielectric layer thereby exposing underside portions of said storage node plate; p) forming a cell dielectric layer superjacent and coextensive said exposed portions of said storage node plate; and q) depositing a second conductive layer superjacent and coextensive said cell dielectric layer, thereby forming a top cell plate, said top cell plate being common to the entire memory array.