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JPS6184024A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: NEC Corp
•
Filing: 1984-10-02
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Granted: —
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Expires: 2004-10-02
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Abstract

Abstract PURPOSE:To provide suitably tapered connection holes uniformly by a method wherein a phosphorus silicate glass (PSG) film, an Si3N4 film, and a BSG film are laminated on a semiconductor substrate successively, a wet etching is performed on the BSG film using a photoresist mask, and a plasma etching is performed on the Si3N4 and the PSG. CONSTITUTION:A PSG film 6, an Si3N4 film 7 and a BSG film 8 are superposed on an Si substrate 5, and a photoresist mask 9 of pattern width W0 is provided. When an etching is performed on the BSG using shock absorbing hydrofluoric acid, the amounts of etching on the side face W1-W0 are remarkably small, because the etching speed of the BSG is extremely lower than that of the PSG, the Si3N4 has a very small etching rate, and the PSG located below the Si3N4 is never etched. Then, after the Si3N4 film 7 and the PSG film 6 are etched by performing an anisotropic etching and the resist 9 is removed, suitably tapered connection holes are obtained mainly on the BSG film 8, and the width of a connection part can be made small by providing an Al wiring 10. As the etching rate of the BSG is low for shock absorbing hydrofluoric acid, the control of taper can be performed freely and the connection holes can be formed uniformly.

Inventors

  • 👤 Akinori Shimizu
  • 👤 清水 明徳

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 00:03
CPC Classifications
H; H10; H10P; H10P50/00

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Total Claims: 0
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