US5384276A
Expired / Lapsed
US
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Method of fabricating a memory device with a multilayer insulating film
Assignee: Panasonic Holdings Corp
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Filing: 1992-07-02
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Granted: 1995-01-24
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Expires: 2012-07-02
Abstract
Abstract A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.
Inventors
- 👤 Hisashi Ogawa
- 👤 Yutaka Nabeshima
- 👤 Masanori Fukumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/714; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10D1/716; Y; Y10; Y10S; Y10S148/00; Y10S148/014
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
121 words
A method of fabricating a semiconductor device, comprising the steps of: forming switching transistors on a semiconductor substrate; forming on the semiconductor substrate an insulating film to cover said switching transistors; forming on said insulating film a multi-layer film consisting of two or more kinds of insulating layers; performing first etching to form contact holes in said multi-layer film and said insulating film, said contact holes reaching active regions of said switching transistors; performing second etching to etch the sides of said multi-layer film and said insulating film and thereby forming grooves in the sides thereof; forming a conductive film to cover said sides of said multi-layer film and said insulating film; and performing third etching to remove said multi-layer film.
Claim 2
Independent Claim
121 words
A method of fabricating a semiconductor device, comprising the steps of: forming switching transistors on a semiconductor substrate; forming on the semiconductor substrate an insulating film to cover said switching transistors; forming on said insulating film a multi-layer film consisting of two or more kinds of insulating layers; performing first etching to form contact holes in said multi-layer film and said insulating film, said contact holes reaching active regions of said switching transistors; performing second etching to etch the sides of said multi-layer film and said insulating film and thereby forming grooves in the sides thereof; forming a conductive film to cover said sides of said multi-layer film and said insulating film; and performing third etching to remove said multi-layer film.
Claim 3
Dependent Claim
39 words
A method according to claim 1, wherein the step of forming said multi-layer film on said insulating film comprises a step of successively depositing two or more insulating layers having different concentrations of impurity by using a CVD technique.
Claim 4
Dependent Claim
39 words
A method according to claim 1, wherein the step of forming said multi-layer film on the insulating film comprises a step of successively depositing two or more insulating layers containing different kinds of impurities by using a CVD technique.
Claim 5
Dependent Claim
25 words
A method according to claim 2 or 3, wherein said first etching is an anisotropic dry etching and said second etching is an isotropic etching.
References Cited (Backward Citations)
JPS63293967A
Cited
US5071783A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
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