Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node

Claim 2

A process for fabricating a conductive container structure on a starting substrate, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conductive spacer adjacent the wall of said container form, said conductive spacer having inner and outer surfaces; g) removing said second insulating layer thereby exposing said outer surface of said conductive spacer; h) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said conductive spacer; i) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; j) patterning said hemispherical grained conductive material to form a separate conductive container structure; k) removing said insulating spacers; l) forming a third insulating layer adjacent and coextensive said conductive container structure and said first insulating layer; and m) forming a second conductive layer superjacent and coextensive said third insulating layer.

Claim 3

A process as recited in claim 1, wherein said conductive plug comprises conductively doped polysilicon.

Claim 4

A process as recited in claim 1, wherein said first insulating layer is silicon nitride.

Claim 5

A process as recited in claim 1, wherein said second insulating layer is silicon oxide.

Claim 6

A process as recited in claim 1, wherein said conductive spacer comprises conductively doped polysilicon.

Claim 7

A process as recited in claim 1, wherein said hemispherical grained conductive material comprises conductively doped hemispherical grained polysilicon.

Claim 8

A process as recited in claim 1, wherein said insulating spacers are silicon oxide.

Claim 9

A process as recited in claim 1, wherein said third insulating layer is silicon nitride.

Claim 10

A process as recited in claim 1, wherein said second conductive layer comprises conductively doped polysilicon.

Claim 11

A process for fabricating a conductive double container structure on a starting substrate, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conformal conductive layer adjacent the wall of said container form; g) forming a third insulating layer; h) removing portions of said third insulating layer and said conductive layer such that said conductive layer is separated into L-shaped structures, said L-shaped conductive structures having inner and outer surfaces with vertical insulating spacers adjacent the inner portions of said L-shaped structures; i) forming a conductive plug between said insulating spacers, said conductive plug making contact to said L-shaped structures and said first conductive plug; j) removing said insulating spacers and said second insulating layer, thereby exposing said inner and outer surfaces of said L-shaped structures k) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said L-shaped structures; l) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; m) patterning said hemispherical grained conductive material to form a separate conductive double container structure; n) removing said insulating spacers; o) forming a third insulating layer adjacent and coextensive said conductive double container structure and said first insulating layer; and p) forming a second conductive layer superjacent and coextensive said third insulating layer

Claim 12

A process for fabricating a conductive double container structure on a starting substrate, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conformal conductive layer adjacent the wall of said container form; g) forming a third insulating layer; h) removing portions of said third insulating layer and said conductive layer such that said conductive layer is separated into L-shaped structures, said L-shaped conductive structures having inner and outer surfaces with vertical insulating spacers adjacent the inner portions of said L-shaped structures; i) forming a conductive plug between said insulating spacers, said conductive plug making contact to said L-shaped structures and said first conductive plug; j) removing said insulating spacers and said second insulating layer, thereby exposing said inner and outer surfaces of said L-shaped structures k) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said L-shaped structures; l) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; m) patterning said hemispherical grained conductive material to form a separate conductive double container structure; n) removing said insulating spacers; o) forming a third insulating layer adjacent and coextensive said conductive double container structure and said first insulating layer; and p) forming a second conductive layer superjacent and coextensive said third insulating layer

Claim 13

A process as recited in claim 10, wherein said first conductive plug comprises conductively doped polysilicon.

Claim 14

A process as recited in claim 10, wherein said first insulating layer is silicon nitride.

Claim 15

A process as recited in claim 10, wherein said second insulating layer is silicon oxide.

Claim 16

A process as recited in claim 10, wherein said conformal conductive layer comprises conductively doped polysilicon.

Claim 17

A process as recited in claim 10, wherein said third insulating layer is silicon oxide.

Claim 18

A process as recited in claim 10, wherein said second conductive plug comprises conductively doped polysilicon.

Claim 19

A process as recited in claim 10, wherein said hemispherical grained conductive material comprises conductively doped hemispherical grained polysilicon.

Claim 20

A process as recited in claim 10, wherein said insulating spacers are silicon oxide.

Claim 21

A process as recited in claim 10, wherein said third insulating layer is silicon nitride.

Claim 22

A process as recited in claim 10, wherein said second conductive layer comprises conductively doped polysilicon.

Claim 23

A process for fabricating a DRAM container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive word lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conductive spacer adjacent the wall of said container form, said conductive spacer having inner and outer surfaces; g) removing said second insulating layer, thereby exposing said outer surface of said conductive spacer; h) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said conductive spacer; i) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; j) patterning said hemispherical grained conductive material to form a separate conductive container structure serving as a first capacitor cell plate; k) removing said insulating spacers; l) forming a capacitor cell dielectric layer adjacent and coextensive said conductive container structure and said first insulating layer; and m) forming a second conductive layer superjacent and coextensive said capacitor cell dielectric layer, said second conductive layer forming a second capacitor cell plate.

Claim 24

A process for fabricating a DRAM container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive word lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conductive spacer adjacent the wall of said container form, said conductive spacer having inner and outer surfaces; g) removing said second insulating layer, thereby exposing said outer surface of said conductive spacer; h) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said conductive spacer; i) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; j) patterning said hemispherical grained conductive material to form a separate conductive container structure serving as a first capacitor cell plate; k) removing said insulating spacers; l) forming a capacitor cell dielectric layer adjacent and coextensive said conductive container structure and said first insulating layer; and m) forming a second conductive layer superjacent and coextensive said capacitor cell dielectric layer, said second conductive layer forming a second capacitor cell plate.

Claim 25

A process as recited in claim 21, wherein said conductive plug comprises conductively doped polysilicon.

Claim 26

A process as recited in .claim 21, wherein said first insulating layer is silicon nitride.

Claim 27

A process as recited in claim 21, wherein said second insulating layer is silicon oxide.

Claim 28

A process as recited in claim 21, wherein said conductive spacer comprises conductively doped polysilicon.

Claim 29

A process as recited in claim 21, wherein said hemispherical grained conductive material comprises conductively doped hemispherical grained polysilicon.

Claim 30

A process as recited in claim 21, wherein said insulating spacers are silicon oxide.

Claim 31

A process as recited in claim 21, wherein said third insulating layer is silicon nitride.

Claim 32

A process as recited in claim 21, wherein said second conductive layer comprises conductively doped polysilicon.

Claim 33

A process for fabricating a DRAM double container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive word lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conformal conductive layer adjacent the wall of said container form; g) forming a third insulating layer; h) etching said third insulating layer and said conductive layer such that said conductive layer is separated into L-shaped structures, said L-shaped conductive structures having inner and outer surfaces with vertical insulating spacers adjacent the inner portions of said L-shaped structures; i) forming a conductive plug between said insulating spacers, said conductive plug making contact to said L-shaped structures and said first conductive plug; j) removing said insulating spacers and said second insulating layer, thereby exposing said inner and outer surfaces of said L-shaped structures; k) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said L-shaped structures; l) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; m) patterning said hemispherical grained conductive material to form a separate conductive double container structure serving as a first capacitor cell plate; n) removing said insulating spacers; o) forming a capacitor cell dielectric layer adjacent and coextensive said conductive double container structure and said first insulating layer; and p) forming a second conductive layer superjacent and coextensive said capacitor cell dielectric layer, said second conductive layer forming a second capacitor cell plate.

Claim 34

A process for fabricating a DRAM double container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: a) forming a first insulating layer over parallel conductive lines; b) forming an opening through said first insulating layer between neighboring parallel conductive lines; c) forming a conductive plug between said neighboring parallel conductive word lines; d) forming a planarized blanketing second insulating layer over said first insulative layer and said conductive plug; e) forming an opening into said second insulating layer, said opening thereby forming a container shape; f) forming a conformal conductive layer adjacent the wall of said container form; g) forming a third insulating layer; h) etching said third insulating layer and said conductive layer such that said conductive layer is separated into L-shaped structures, said L-shaped conductive structures having inner and outer surfaces with vertical insulating spacers adjacent the inner portions of said L-shaped structures; i) forming a conductive plug between said insulating spacers, said conductive plug making contact to said L-shaped structures and said first conductive plug; j) removing said insulating spacers and said second insulating layer, thereby exposing said inner and outer surfaces of said L-shaped structures; k) forming a layer of hemispherical grained conductive material superjacent said inner and outer surfaces of said L-shaped structures; l) forming insulating spacers adjacent the inner and outer surfaces of said hemispherical grained conductive material; m) patterning said hemispherical grained conductive material to form a separate conductive double container structure serving as a first capacitor cell plate; n) removing said insulating spacers; o) forming a capacitor cell dielectric layer adjacent and coextensive said conductive double container structure and said first insulating layer; and p) forming a second conductive layer superjacent and coextensive said capacitor cell dielectric layer, said second conductive layer forming a second capacitor cell plate.

Claim 35

A process as recited in claim 30, wherein said first conductive plug comprises conductively doped polysilicon.

Claim 36

A process as recited in claim 30, wherein said first insulating layer is silicon nitride.

Claim 37

A process as recited in claim 30, wherein said second insulating layer is silicon oxide.

Claim 38

A process as recited in claim 30, wherein said conformal conductive layer comprises conductively doped polysilicon.

Claim 39

A process as recited in claim 30, wherein said third insulating layer is silicon oxide.

Claim 40

A process as recited in claim 30, wherein said second conductive plug comprises conductively doped polysilicon.

Claim 41

A process as recited in claim 30, wherein said hemispherical grained conductive material comprises conductively doped hemispherical grained polysilicon.

Claim 42

A process as recited, in claim 30, wherein said insulating spacers are silicon oxide.

Claim 43

A process as recited in claim 30, wherein said third insulating layer is silicon nitride.

Claim 44

A process as recited in claim 30, wherein said second conductive layer comprises conductively doped polysilicon.