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US4874719A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing an electrical connection between conductor levels

Assignee: Toshiba Corp
•
Filing: 1988-07-18
•
Granted: 1989-10-17
•
Expires: 2008-07-18
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Abstract

Abstract Disclosed is a method for making connection between conductor layers through a contact via comprising the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming an insulation interlayer so that it covers the first conductive pattern, (c) forming, on the insulation interlayer, a conductive film of which a second conductive pattern is formed, (d) forming a contact hole, at a predetermined location, in both the conductive film and the insulation interlayer, so that the contact hole reaches the first conductive pattern, (e) forming the conductive layer at least in the contact hole, to make an electrical connection between the conductive film and the first conductive pattern, and (f) subsequent to the formation of the conductive film by step (e), selectively etching the conductive film and the conductive layer, to form said second conductive pattern. In an alternative embodiment, the second conductive pattern is obtained by selectively etching the conductive film prior to the formation of the contact hole, and the electrical connection is formed by selective CVD.

Inventors

  • 👤 Kei Kurosawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 05:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/026

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 142 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first conductive pattern; (b) forming an insulation interlayer so that it covers the first conductive pattern; (c) forming, on the insulation interlayer, a conductive film on which a second conductive pattern is formed; (d) forming a contact hole, at a predetermined location, in both said conductive film and said insulation interlayer, so that said contact hole reaches said first conductive pattern; (e) forming a conductive layer for both covering the interior of the contact hole and directly covering the upper surface of the conductive film, so that a wiring is made between the conductive film and the first conductive pattern; and (f) subsequent to the formation of said conductive layer by step (e), selectively etching said conductive film and said conductive layer, to form the second conductive pattern.
Claim 2
Independent Claim 142 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first conductive pattern; (b) forming an insulation interlayer so that it covers the first conductive pattern; (c) forming, on the insulation interlayer, a conductive film on which a second conductive pattern is formed; (d) forming a contact hole, at a predetermined location, in both said conductive film and said insulation interlayer, so that said contact hole reaches said first conductive pattern; (e) forming a conductive layer for both covering the interior of the contact hole and directly covering the upper surface of the conductive film, so that a wiring is made between the conductive film and the first conductive pattern; and (f) subsequent to the formation of said conductive layer by step (e), selectively etching said conductive film and said conductive layer, to form the second conductive pattern.
Claim 3
Dependent Claim 22 words
The method according to claim 1, wherein said step for forming a conductive layer is performed by use of the CVD method.
Claim 4
Dependent Claim 14 words
The method according to claim 2, wherein poly-Si is used as said conductive layer.
Claim 5
Dependent Claim 18 words
The method according to claim 3, wherein Al issued as said conductive film for said second conductive pattern.
Claim 6
Dependent Claim 22 words
The method according to claim 3, wherein an MoSi 2 film is used as said conductive film for said second conductive pattern.
Claim 7
Dependent Claim 16 words
The method according to claim 5, wherein said second conductive pattern is a DRAM bit line.
Claim 8
Dependent Claim 24 words
The method according to claim 1, wherein said conductive layer is formed so that said contact hole is completely filled with said conductive layer.
Claim 9
Dependent Claim 16 words
The method according to claim 1, wherein said first conductive pattern is a first wiring layer.
Claim 10
Dependent Claim 21 words
The method according to claim 1, wherein said first conductive pattern is an impurity diffusion layer formed in a semiconductor layer.

References Cited (Backward Citations)

US4322736A Cited
US4403394A Cited
US4619037A Cited
US4441247A Cited
US4582563A Cited
US4581623A Cited
US4616401A Cited
US4663831A Cited
US4696097A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-10-16 1993-04-17 1993-10-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-10-16 1997-04-17 1997-10-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-10-16 2001-04-17 2001-10-17 $7700.00 Window Closed / Lapsed

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