Method of fabricating an insulated gate type field-effect transistor

Claim 1

A method of fabricating an insulated gate type field-effect transistor, comprising the steps of: forming a gate electrode on a gate insulating film and patterned by selective etching using a masking member, said gate insulating film being formed on a semiconductor region of a substrate surrounded by a field insulating film; forming source and drain regions aligned to said gate electrode by doping impurities into the semiconductor region; forming a first insulating film on the entire surface of the substrate by chemical vapor depositon; etching the first insulating film by reactive ion etching, except for the portions of the first insulating film that are formed on both sides of a laminate consisting of the masking member and the gate electrode; removing said masking member, thereby exposing said gate electrode; forming conductive material films by selective chemical vapor deposition on the exposed surfaces of said gate electrode, said source and drain regions and regions surrounding said source and drain regions extending onto said field insulating film; forming a second insulating film on the entire surface of the substrate including said conductive material films; forming contact holes in those portions of said second insulating film which are positioned above said gate electrode and said source and drain regions; and forming interconnection layers contacting said conductive material films exposed through said contact holes.

Claim 2

A method of fabricating an insulated gate type field-effect transistor, comprising the steps of: forming a gate electrode on a gate insulating film and patterned by selective etching using a masking member, said gate insulating film being formed on a semiconductor region of a substrate surrounded by a field insulating film; forming source and drain regions aligned to said gate electrode by doping impurities into the semiconductor region; forming a first insulating film on the entire surface of the substrate by chemical vapor depositon; etching the first insulating film by reactive ion etching, except for the portions of the first insulating film that are formed on both sides of a laminate consisting of the masking member and the gate electrode; removing said masking member, thereby exposing said gate electrode; forming conductive material films by selective chemical vapor deposition on the exposed surfaces of said gate electrode, said source and drain regions and regions surrounding said source and drain regions extending onto said field insulating film; forming a second insulating film on the entire surface of the substrate including said conductive material films; forming contact holes in those portions of said second insulating film which are positioned above said gate electrode and said source and drain regions; and forming interconnection layers contacting said conductive material films exposed through said contact holes.