Stacked comb spacer capacitor

Claim 2

A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: creating a plurality of separately isolated active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns; creating a gate dielectric layer on top of each active area; depositing a first conductive layer superjacent surface of said array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer; creating of a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; depositing a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; depositing a third dielectric layer superjacent to said second conductive layer; masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology; depositing a first oxide layer superjacent said array surface of said waveform-like topology; creating a second aligned buried contact location at each said storage node junction in each said active area; depositing a third conductive layer superjacent said array surface assuming said waveform-like topology in response to existing topology, said third conductive layer making contact to said storage node junctions at said second buried contact locations; depositing a fourth dielectric layer; patterning said fourth dielectric layer to form a comb dielectric running parallel to said word lines; depositing a fourth conductive layer conformal to existing topology, said fourth conductive layer attaching to said third conductive layer; etching said fourth conductive layer thereby forming vertically spiked polysilicon spacer walls; etching said fourth dielectric; masking said third and said fourth conductive layers with resist; etching exposed area of said third conductive layer, said third conductive layer having a v-shaped cross-section, said third and said fourth conductive layers thereby forming a completed storage node plate having a spiked v-shaped cross-section; removing said resist; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a fourth conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.

Claim 3

A process as recited in claim 1, wherein said gate dielectric layer is oxide.

Claim 4

A process as recited in claim 1, wherein said first and said second conductive layers comprise a layer of tungsten silicide and doped polysilicon.

Claim 5

A process as recited in claim 1, wherein said first, said second, and said fourth dielectric layers are selected from the group consisting essentially of oxide or nitride.

Claim 6

A process as recited in claim 1, wherein said third dielectric layer is oxide.

Claim 7

A process as recited in claim 1, wherein said first and said second buried contacts are self aligned.

Claim 8

A process as recited in claim 1, wherein said third, said fourth and said fifth conductive layers are doped polysilicon.

Claim 9

A process as recited in claim 1, wherein said third and said fourth conductive layers are deposited by low temperature deposition.

Claim 10

A process as recited in claim 1, wherein said second, said third, and said fourth dielectric layers are deposited by chemical vapor deposition.

Claim 11

A process as recited in claim 1, wherein said cell dielectric layer is nitride.

Claim 12

A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: creating a plurality of separately isolated active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns; creating a gate dielectric layer on top of each active area; depositing a first conductive layer superjacent surface of said array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer; creating of a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; depositing a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; depositing a third dielectric layer superjacent to said second conductive layer; masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology; depositing a fourth dielectric layer superjacent said array surface of said waveform-like topology, said fourth dielectric layer comprising a first nitride layer superjacent to said array surface and a first oxide layer superjacent said first nitride layer; creating a second aligned buried contact location at each said storage node junction in each said active area; depositing a third conductive layer superjacent said array surface assuming said waveform-like topology in response to existing topology, said third conductive layer making contact to said storage node junctions at said second buried contact locations; depositing a fifth dielectric layer; patterning said fifth dielectric layer to form a comb dielectric running parallel to said word lines; depositing a fourth conductive layer conformal to existing topology, said fourth conductive layer attaching to said third conductive layer; etching said fourth conductive layer thereby forming vertically spiked polysilicon spacer walls; etching said fifth dielectric; masking said third and said fourth conductive layers with resist; etching exposed area of said third conductive layer, said third conductive layer having a v-shaped cross-section, said third and said fourth conductive layers thereby forming a completed storage node plate having a spiked v-shaped cross-section; removing said resist; etching said first oxide layer of said fourth dielectric layer thereby exposing a backside of said storage node cell plate; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a fourth conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.

Claim 13

A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: creating a plurality of separately isolated active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns; creating a gate dielectric layer on top of each active area; depositing a first conductive layer superjacent surface of said array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer; creating of a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; depositing a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; depositing a third dielectric layer superjacent to said second conductive layer; masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology; depositing a fourth dielectric layer superjacent said array surface of said waveform-like topology, said fourth dielectric layer comprising a first nitride layer superjacent to said array surface and a first oxide layer superjacent said first nitride layer; creating a second aligned buried contact location at each said storage node junction in each said active area; depositing a third conductive layer superjacent said array surface assuming said waveform-like topology in response to existing topology, said third conductive layer making contact to said storage node junctions at said second buried contact locations; depositing a fifth dielectric layer; patterning said fifth dielectric layer to form a comb dielectric running parallel to said word lines; depositing a fourth conductive layer conformal to existing topology, said fourth conductive layer attaching to said third conductive layer; etching said fourth conductive layer thereby forming vertically spiked polysilicon spacer walls; etching said fifth dielectric; masking said third and said fourth conductive layers with resist; etching exposed area of said third conductive layer, said third conductive layer having a v-shaped cross-section, said third and said fourth conductive layers thereby forming a completed storage node plate having a spiked v-shaped cross-section; removing said resist; etching said first oxide layer of said fourth dielectric layer thereby exposing a backside of said storage node cell plate; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a fourth conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.

Claim 14

A process as recited in claim 11, wherein said gate dielectric layer is oxide.

Claim 15

A process as recited in claim 11, wherein said first and said second conductive layers comprise a layer of tungsten silicide and doped polysilicon.

Claim 16

A process as recited in claim 11, wherein said first, said second, and said fifth dielectric layers are selected from the group consisting essentially of oxide or nitride.

Claim 17

A process as recited in claim 11 wherein said third dielectric layer is oxide.

Claim 18

A process as recited in claim 11, wherein said first and said second buried contacts are self aligned.

Claim 19

A process as recited in claim 11, wherein said third, said fourth and said fifth conductive layers are doped polysilicon.

Claim 20

A process as recited in claim 11, wherein said third and said fourth conductive layers are deposited by low temperature deposition.

Claim 21

A process as recited in claim 11, wherein said second, said third, and said fourth dielectric layers are deposited by chemical vapor deposition.

Claim 22

A process as recited in claim 11, wherein said cell dielectric layer is nitride.