US5139967A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for planarizing insulating dielectric material
Assignee: Micron Technology Inc
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Filing: 1991-02-20
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Granted: 1992-08-18
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Expires: 2011-02-20
Abstract
Abstract A method of processing a semiconductor wafer comprises the following sequential steps: selectively fabricating a semiconductor wafer in multilevels to produce desired electronic devices and integrated circuits on the wafer, the selective fabrication resulting in an irregular upper surface topography; applying a coating of insulating dielectric material having a melting point of less than or equal to about 850 DEG C. atop the fabricated wafer; and selectively impinging laser energy upon the dielectric coating for a selected period of time to at least partially melt the dielectric coating and cause its upper surface to become planarized.
Inventors
- 👤 Gurtej S. Sandhu
- 👤 Trung T. Doan
- 👤 Chang Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:00
CPC Classifications
H; H10; H10P; H10P95/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
138 words
A method of processing a semiconductor wafer comprising the following sequential steps: selectively fabricating a semiconductor wafer in multilevels to produce desired completed electronic devices and integrated circuits on the wafer, the selective fabrication resulting in an irregular upper surface topography having high and low points separated from one another by at least one micron; applying a protective coating of borophosphosilicate glass insulating dielectric material having a melting point of less than or equal to about 850° C. atop the fabricated wafer; and selectively impinging excimer laser energy directly upon the protective insulating coating at a fluence of from 0.5 Joules/cm 2 to 10.0 Joules/cm 2 with intermittent pulses having a pulse on period of approximately 25 nanoseconds for a selected period of time to melt the protective insulating coating and cause its upper surface to become planarized.
Claim 2
Independent Claim
138 words
A method of processing a semiconductor wafer comprising the following sequential steps: selectively fabricating a semiconductor wafer in multilevels to produce desired completed electronic devices and integrated circuits on the wafer, the selective fabrication resulting in an irregular upper surface topography having high and low points separated from one another by at least one micron; applying a protective coating of borophosphosilicate glass insulating dielectric material having a melting point of less than or equal to about 850° C. atop the fabricated wafer; and selectively impinging excimer laser energy directly upon the protective insulating coating at a fluence of from 0.5 Joules/cm 2 to 10.0 Joules/cm 2 with intermittent pulses having a pulse on period of approximately 25 nanoseconds for a selected period of time to melt the protective insulating coating and cause its upper surface to become planarized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |