US5639685A
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US
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Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon
Assignee: Micron Technology Inc
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Filing: 1995-10-06
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Granted: 1997-06-17
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Expires: 2015-10-06
Abstract
Abstract A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350° C. to about 600° C. and at an annealing pressure of from about 10 -4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
Inventors
- 👤 John K. Zahurak
- 👤 Klaus F. Schuegraf
- 👤 Randhir P. S. Thakur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:34
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; Y; Y10; Y10S; Y10S148/00; Y10S148/138
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
93 words
A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: depositing a layer of non-polycrystalline silicon over the substrate to a thickness of less than or equal to about 400 Angstroms; and annealing the substrate having the deposited non-polycrystalline silicon layer within a chemical vapor deposition reactor in the presence of a conductivity enhancing impurity gas under conditions effective to in situ both diffuse conductivity enhancing impurity into the layer and transform the silicon into a conductively doped hemispherical grain polysilicon layer.
Claim 2
Dependent Claim
93 words
A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: depositing a layer of non-polycrystalline silicon over the substrate to a thickness of less than or equal to about 400 Angstroms; and annealing the substrate having the deposited non-polycrystalline silicon layer within a chemical vapor deposition reactor in the presence of a conductivity enhancing impurity gas under conditions effective to in situ both diffuse conductivity enhancing impurity into the layer and transform the silicon into a conductively doped hemispherical grain polysilicon layer.
Claim 3
Dependent Claim
22 words
The semiconductor processing method of claim 1 wherein the depositing and annealing steps are conducted in the same chemical vapor deposition reactor.
Claim 4
Dependent Claim
26 words
The semiconductor processing method of claim 1 wherein the non-polycrystalline silicon layer is deposited to a thickness of greater than or equal to about 100 Angstroms.
Claim 5
Dependent Claim
21 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature of at least about 350° C.
Claim 6
Dependent Claim
40 words
The semiconductor processing method of claim 1 wherein the non-polycrystalline silicon layer is deposited to a thickness of greater than or equal to about 100 Angstroms; and the effective annealing conditions comprise a temperature of at least about 350° C.
Claim 7
Dependent Claim
23 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature from about 350° C. to about 600° C.
Claim 8
Dependent Claim
23 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.
Claim 9
Dependent Claim
24 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr.
Claim 10
Dependent Claim
38 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, and the effective annealing conditions comprise a temperature of at least about 350° C.
Claim 11
Dependent Claim
40 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, and the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.
Claim 12
Dependent Claim
83 words
The semiconductor processing method of claim 1 further comprising the following steps conducted sequentially between the depositing and annealing steps within the chemical vapor deposition reactor with the substrate positioned therein: lowering pressure within the chemical vapor deposition reactor to a first pressure; raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; and ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure.
Claim 13
Dependent Claim
21 words
The semiconductor processing method of claim 11 wherein the first and second pressures are each at or below about 200 mTorr.
Claim 14
Dependent Claim
116 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.; and further comprising the following steps conducted sequentially between the depositing and annealing steps within the chemical vapor deposition reactor with the substrate positioned therein: lowering pressure within the chemical vapor deposition reactor to a first pressure; raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; and ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure.
Claim 15
Dependent Claim
21 words
The semiconductor processing method of claim 1 wherein the non-polycrystalline silicon layer as deposited is completely without conductivity enhancing impurity dopant.
Claim 16
Dependent Claim
12 words
The semiconductor processing method of claim 1 wherein the substrate comprises silicon.
Claim 17
Dependent Claim
12 words
The semiconductor processing method of claim 1 wherein the substrate comprises polysilicon.
Claim 18
Dependent Claim
62 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions include an annealing temperature, the method further comprising: after the annealing step, raising the temperature of the substrate within the reactor from the annealing temperature and providing a conductivity enhancing impurity gas within the reactor under conditions effective to diffuse more conductivity enhancing impurity into the hemispherical grain polysilicon layer.
Claim 19
Dependent Claim
80 words
The semiconductor processing method of claim 1 wherein the non-polycrystalline silicon layer is deposited to a thickness of greater than or equal to about 100 Angstroms, the effective annealing conditions include an annealing temperature, the method further comprising: after the annealing step, raising the temperature of the substrate within the reactor from the annealing temperature and providing a conductivity enhancing impurity gas within the reactor under conditions effective to diffuse more conductivity enhancing impurity into the hemispherical grain polysilicon layer.
Claim 20
Dependent Claim
69 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a temperature from about 550° C. to about 600° C., the method further comprising: after the annealing step, raising the temperature of the substrate within the reactor from the annealing temperature and providing a conductivity enhancing impurity gas within the reactor under conditions effective to diffuse more conductivity enhancing impurity into the hemispherical grain polysilicon layer.
Claim 21
Dependent Claim
159 words
The semiconductor processing method of claim 1 wherein the effective annealing conditions comprise a pressure from about 10 -4 Torr to about 80 Torr, the effective annealing conditions comprise a temperature from about 550° C. to about 600° C.; and further comprising the following steps conducted sequentially between the depositing and annealing steps within the chemical vapor deposition reactor with the substrate positioned therein: lowering pressure within the chemical vapor deposition reactor to a first pressure; raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; and ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure; and after the annealing step, raising the temperature of the substrate within the reactor from the annealing temperature and providing a conductivity enhancing impurity gas within the reactor under conditions effective to diffuse more conductivity enhancing impurity into the hemispherical grain polysilicon layer.
Claim 22
Dependent Claim
229 words
A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: providing a layer of conductively doped silicon over the substrate to a thickness greater than about 100 Angstroms; depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350° C. to about 600° C. and at an annealing pressure of from about 10 -4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
Claim 23
Dependent Claim
229 words
A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate comprising the following steps: providing a layer of conductively doped silicon over the substrate to a thickness greater than about 100 Angstroms; depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350° C. to about 600° C. and at an annealing pressure of from about 10 -4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
Claim 24
Dependent Claim
22 words
The semiconductor processing method of claim 21 wherein the doped silicon layer comprises polycrystalline silicon both before and after the annealing step.
Claim 25
Dependent Claim
51 words
The semiconductor processing method of claim 21 further comprising: after the annealing step, raising the temperature of the substrate within the reactor from the annealing temperature and providing a conductivity enhancing impurity gas within the reactor under conditions effective to diffuse more conductivity enhancing impurity into the hemispherical grain polysilicon layer.
Claim 26
Dependent Claim
67 words
The semiconductor processing method of claim 21 wherein the doped silicon layer comprises polycrystalline silicon both before and after the annealing step, and further comprising: after the annealing step, raising the temperature of the substrate within the reactor from the annealing temperature and providing a conductivity enhancing impurity gas within the reactor under conditions effective to diffuse more conductivity enhancing impurity into the hemispherical grain polysilicon layer.
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