Method of making cup-shaped DRAM capacitor having an inwardly overhanging lip

Claim 2

A process for forming a capacitor for use in an integrated circuit, said process comprising the following steps: (a) providing a mold stratum which comprises at least one layer, said mold layer having an upper surface; (b) forming a cavity in the mold stratum, said cavity having both a bottom portion and a perimetric wall portion, said wall portion having a perimetric, inwardly-overhanging lip at an uppermost end; (c) lining the cavity with a first capacitive plate layer; (d) forming a dielectric layer which coats at least a portion of said first capacitive plate layer; and (e) forming a second capacitive plate that is insulated from said first capacitive plate by said dielectric layer.

Claim 3

The process of claim 1, wherein the mold stratum is formed by depositing an etch stop layer on top of a mold layer.

Claim 4

The process of claim 2, wherein the cavity is formed via the following steps: (a) downwardly etching through both the etch-stop layer and the mold layer; and (b) performing an isotropic etch which undercuts the mold layer in the cavity beneath the etch-stop layer so that a portion of the etch-stop layer that is perimetric to the cavity forms an inwardly-overhanging lip.

Claim 5

The process of claim 3, wherein lining the cavity with a first capacitive plate layer is accomplished via the following steps: (a) depositing a first capacitive layer, which covers an upper surface of the etch-stop layer, wraps around the overhanging lip, and covers both the floor and wall portions of the cavity; and (b) performing a plasma etch which stops on the upper surface of the etch-stop layer.

Claim 6

The process of claim 4, which further comprises the step of removing the etch-stop layer following the plasma etch.

Claim 7

The process of claim 3, wherein a remaining portion of the mold layer is completely removed following removal of the etch stop layer.

Claim 8

The process of claim 1, wherein said first and second capacitive plates are formed from doped silicon layers deposited via chemical vapor deposition.

Claim 9

The process of claim 1, wherein said first capacitive plate is formed by depositing an amorphous silicon layer and subsequently annealing the amorphous silicon layer in order to convert it to a hemispherical grain polycrystalline silicon layer.

Claim 10

A process for fabricating cell capacitors for an in-process dynamic random access memory array, said in-process array having an access transistor for each cell within the array, each transistor having a pair of source/drain regions, one of which is designated as an access-node junction for bitline contact, and the other of which is designated as a storage-node junction for electrical contact to one plate of a cell capacitor, said process comprising the steps of: (a) depositing a mold layer over the in-process array; (b) depositing an etch stop layer on an upper surface of the mold layer; (c) forming a channel through both the etch-stop layer and the mold layer for each cell, each channel having a perimetric wall that is normal to the upper surface of the mold layer, each channel being vertically aligned with and superjacent the storage-node junction of its respective cell; (d) providing, at the bottom of each channel, means for making electrical contact to the subjacent storage-node junction; (e) performing an isotropic etch which undercuts the mold layer beneath the etch-stop layer within each channel so that a portion of the etch-stop layer that is perimetric to each channel opening forms an overhanging lip; (f) depositing a first capacitive layer, which covers an upper surface of the etch-stop layer, wraps around each overhanging lip, and lines the entire channel interior; (g) performing a plasma etch which stops on the upper surface of the etch-stop layer; (h) removing the etch-stop layer; (i) forming a cell dielectric layer; and (j) depositing a second capacitive layer.

Claim 11

A process for fabricating cell capacitors for an in-process dynamic random access memory array, said in-process array having an access transistor for each cell within the array, each transistor having a pair of source/drain regions, one of which is designated as an access-node junction for bitline contact, and the other of which is designated as a storage-node junction for electrical contact to one plate of a cell capacitor, said process comprising the steps of: (a) depositing a mold layer over the in-process array; (b) depositing an etch stop layer on an upper surface of the mold layer; (c) forming a channel through both the etch-stop layer and the mold layer for each cell, each channel having a perimetric wall that is normal to the upper surface of the mold layer, each channel being vertically aligned with and superjacent the storage-node junction of its respective cell; (d) providing, at the bottom of each channel, means for making electrical contact to the subjacent storage-node junction; (e) performing an isotropic etch which undercuts the mold layer beneath the etch-stop layer within each channel so that a portion of the etch-stop layer that is perimetric to each channel opening forms an overhanging lip; (f) depositing a first capacitive layer, which covers an upper surface of the etch-stop layer, wraps around each overhanging lip, and lines the entire channel interior; (g) performing a plasma etch which stops on the upper surface of the etch-stop layer; (h) removing the etch-stop layer; (i) forming a cell dielectric layer; and (j) depositing a second capacitive layer.

Claim 12

The process of claim 9, wherein the base dielectric layer and mold layer both comprise borophosphosilicate glass.(BPSG).

Claim 13

The process of claim 9, wherein a remaining portion of the mold layer are etched away between steps (h) and (i).

Claim 14

The process of claim 9, wherein the array is coated with a planarized photoresist layer between steps (f) and (g).

Claim 15

The process of claim 9, wherein said first and second capacitive layers comprise polycrystalline silicon which is deposited via chemical vapor deposition.

Claim 16

The process of claim 9, wherein the provision of means for making electrical contact to the storage-node junction at the bottom of each mold opening includes the step of fabricating conductive plugs within a base dielectric layer which is deposited between the source/drain regions and the mold layer.

Claim 17

The process of claim 9, wherein means for making electrical contact to the storage-node junction at the bottom of each mold opening is inherent in the process, as no other layers are present between the mold layer and the storage-node junctions.

Claim 18

A process for fabricating a capacitor for use in an integrated circuit constructed on a semiconductor substrate, said process comprising the steps of: (a) depositing a mold layer which overlies the substrate; (b) depositing an etch stop layer on an upper surface of the mold layer; (c) downwardly etching through both the etch-stop layer and the mold layer to form a channel having a floor portion and a perimetric wall portion; (d) performing an isotropic etch which undercuts the mold layer within the channel beneath the etch-stop layer so that a portion of the etch-stop layer that is perimetric to the channel forms an inwardly-overhanging lip; (e) depositing a first capacitive layer, which covers an upper surface of the etch-stop layer, wraps around the overhanging lip, and covers both the floor and wall portions of the channel; (f) performing a plasma etch which stops on the upper surface of the etch-stop layer; (g) removing the etch-stop layer; (h) forming a capacitor dielectric layer; (i) depositing a second capacitive layer, said capacitive layer being insulated from a remaining portion of the first capacitive layer by the capacitor dielectric layer.

Claim 19

A process for fabricating a capacitor for use in an integrated circuit constructed on a semiconductor substrate, said process comprising the steps of: (a) depositing a mold layer which overlies the substrate; (b) depositing an etch stop layer on an upper surface of the mold layer; (c) downwardly etching through both the etch-stop layer and the mold layer to form a channel having a floor portion and a perimetric wall portion; (d) performing an isotropic etch which undercuts the mold layer within the channel beneath the etch-stop layer so that a portion of the etch-stop layer that is perimetric to the channel forms an inwardly-overhanging lip; (e) depositing a first capacitive layer, which covers an upper surface of the etch-stop layer, wraps around the overhanging lip, and covers both the floor and wall portions of the channel; (f) performing a plasma etch which stops on the upper surface of the etch-stop layer; (g) removing the etch-stop layer; (h) forming a capacitor dielectric layer; (i) depositing a second capacitive layer, said capacitive layer being insulated from a remaining portion of the first capacitive layer by the capacitor dielectric layer.

Claim 20

The process of claim 16, wherein the mold layer comprises borophosphosilicate glass.

Claim 21

The process of claim 16, wherein a remaining portion of the mold layer is etched away between steps (g) and (h).

Claim 22

The process of claim 16, wherein downwardly etching is accomplished using a predominantly anisotropic plasma etch.

Claim 23

The process of claim 16, wherein downwardly etching is accomplished using an anisotropic plasma etch.

Claim 24

The process of claim 16, wherein said first and second capacitive layers comprise silicon that is deposited via chemical vapor deposition.

Claim 25

The process of claim 21, wherein said first capacitive layer is formed by depositing an amorphous silicon layer and subsequently annealing the amorphous silicon layer in order to convert it to a hemispherical grain polycrystalline silicon layer.