Corrugated storage contact capacitor and method for forming a corrugated storage contact capacitor

Claim 1

A method for forming at least one capacitor in a semiconductor device having fabricated structures overlying a substrate, the method comprising the following steps: a) depositing an etch stop layer to overlie the fabricated structures and the substrate; b) depositing an insulative layer, said insulative layer overlying said etch stop layer and filling any depressions lying between the fabricated structures; c) planarizing said insulative layer to provide a planar surface overlying the fabricated structures and said etch stop layer; d) alternately depositing of at least a conformal first etch type layer and a conformal second etch type layer, said first etch type layer capable of being substantially more consumed during an etch than said second etch type layer and said insulative layer; e) etching an opening in said first and second etch type layers and said insulative layer in order to expose said etch stop overlying a contact area of said substrate; f) etching a portion of said first etch type layer while substantially retaining said second etch type layer and said insulative layer, and prohibiting etching of the substrate with said etch type layer; g) etching said etch stop in order to expose said contact area; h) depositing a first conductive layer to contact said first and second etch type layers, said insulative layer, and said contact area, said first conductive layer forming a first capacitor plate; i) depositing a dielectric layer to contact said first layer; and j) depositing a second conductive layer to contact said dielectric layer, said second conductive layer forming a second capacitor plate.

Claim 2

A method for forming at least one capacitor in a semiconductor device having fabricated structures overlying a substrate, the method comprising the following steps: a) depositing an etch stop layer to overlie the fabricated structures and the substrate; b) depositing an insulative layer, said insulative layer overlying said etch stop layer and filling any depressions lying between the fabricated structures; c) planarizing said insulative layer to provide a planar surface overlying the fabricated structures and said etch stop layer; d) alternately depositing of at least a conformal first etch type layer and a conformal second etch type layer, said first etch type layer capable of being substantially more consumed during an etch than said second etch type layer and said insulative layer; e) etching an opening in said first and second etch type layers and said insulative layer in order to expose said etch stop overlying a contact area of said substrate; f) etching a portion of said first etch type layer while substantially retaining said second etch type layer and said insulative layer, and prohibiting etching of the substrate with said etch type layer; g) etching said etch stop in order to expose said contact area; h) depositing a first conductive layer to contact said first and second etch type layers, said insulative layer, and said contact area, said first conductive layer forming a first capacitor plate; i) depositing a dielectric layer to contact said first layer; and j) depositing a second conductive layer to contact said dielectric layer, said second conductive layer forming a second capacitor plate.

Claim 5

A method for forming a plurality of capacitors in a semiconductor device comprising the following steps: a) depositing an etch stop layer to overlie previously fabricated structures and a substrate of said semiconductor device; b) depositing at least one insulative layer to overlie said etch stop and to fill in depressions between said previously fabricated structures; c) planarizing said insulative layer to provide a planar surface for conformal depositions; d) alternately depositing at least a conformal first etch type layer and a conformal second etch type layer overlying said insulative layer, said first etch type layer capable of being substantially more consumed during an etch than said second etch type layer and said insulative layer; e) defining self-aligned openings by masking said first and second etch type layers with a patterned photoresist; f) etching said insulative layer and said first and second etch type layers in order to form said openings and expose said etch stop overlying at least a portion of a contact area of said substrate in each of said openings, said openings having sidewalls of said insulative layer and said first and second etch type layers, said sidewalls being substantially normal to a top surface of said substrate; g) etching a portion of said first etch type layer while substantially retaining said second etch type layer and said insulative layer, said etching forming corrugations in said sidewalls; h) etching said etch stop in order to expose said contact area; i) blanket depositing a first capacitive layer to contact said first and second etch type layers and said insulative layer and said contact area; j) masking sad first capacitive layer, said masking defining a plurality of capacitor areas; k) etching said first capacitive layer to separate said first capacitive layer into individual first capacitor plates for each capacitor of said plurality; l) blanket depositing a dielectric layer to overlie at least said individual first capacitor plates; and m) blanket depositing a second capacitive layer to overlie said dielectric layer, said second capacitive layer forming a second capacitor plate of each capacitor of each plurality, said second capacitor plate of each capacitor of said plurality being in electrical communication one with another.

Claim 6

A method for forming a plurality of capacitors in a semiconductor device comprising the following steps: a) depositing an etch stop layer to overlie previously fabricated structures and a substrate of said semiconductor device; b) depositing at least one insulative layer to overlie said etch stop and to fill in depressions between said previously fabricated structures; c) planarizing said insulative layer to provide a planar surface for conformal depositions; d) alternately depositing at least a conformal first etch type layer and a conformal second etch type layer overlying said insulative layer, said first etch type layer capable of being substantially more consumed during an etch than said second etch type layer and said insulative layer; e) defining self-aligned openings by masking said first and second etch type layers with a patterned photoresist; f) etching said insulative layer and said first and second etch type layers in order to form said openings and expose said etch stop overlying at least a portion of a contact area of said substrate in each of said openings, said openings having sidewalls of said insulative layer and said first and second etch type layers, said sidewalls being substantially normal to a top surface of said substrate; g) etching a portion of said first etch type layer while substantially retaining said second etch type layer and said insulative layer, said etching forming corrugations in said sidewalls; h) etching said etch stop in order to expose said contact area; i) blanket depositing a first capacitive layer to contact said first and second etch type layers and said insulative layer and said contact area; j) masking sad first capacitive layer, said masking defining a plurality of capacitor areas; k) etching said first capacitive layer to separate said first capacitive layer into individual first capacitor plates for each capacitor of said plurality; l) blanket depositing a dielectric layer to overlie at least said individual first capacitor plates; and m) blanket depositing a second capacitive layer to overlie said dielectric layer, said second capacitive layer forming a second capacitor plate of each capacitor of each plurality, said second capacitor plate of each capacitor of said plurality being in electrical communication one with another.