Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor

Claim 1

A method of fabricating a semiconductor wafer comprising: providing an electrically conductive area on a semiconductor wafer; providing multiple alternating layers of first and second materials atop the wafer, the first and second materials being selectively etchable relative to one another; etching the multiple layers and upwardly exposing the electrically conductive area, to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area; selectively isotropically etching one of the first or second materials relative to the other of the first and second materials to produce indentations which extend generally laterally into the exposed edges of the multiple layers; applying a layer of electrically conductive material atop the wafer and electrically conductive area, and filling the exposed edge indentations with such electrically conductive material; etching the electrically conductive material to leave conductive material extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations; and etching the multiple layers from the wafer to leave upwardly projecting conductive material having conductive and exposed lateral projections extending therefrom.

Claim 2

A method of fabricating a semiconductor wafer comprising: providing an electrically conductive area on a semiconductor wafer; providing multiple alternating layers of first and second materials atop the wafer, the first and second materials being selectively etchable relative to one another; etching the multiple layers and upwardly exposing the electrically conductive area, to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area; selectively isotropically etching one of the first or second materials relative to the other of the first and second materials to produce indentations which extend generally laterally into the exposed edges of the multiple layers; applying a layer of electrically conductive material atop the wafer and electrically conductive area, and filling the exposed edge indentations with such electrically conductive material; etching the electrically conductive material to leave conductive material extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations; and etching the multiple layers from the wafer to leave upwardly projecting conductive material having conductive and exposed lateral projections extending therefrom.

Claim 14

A method of fabricating a semiconductor wafer comprising: providing an electrically conductive area on a semiconductor wafer; providing multiple alternating layers of oxide and nitride materials atop the wafer to respective thicknesses of from 200 Angstroms to 1000 Angstroms, the oxide and nitride materials being selectively etchable relative to one another; etching the multiple layers and upwardly exposing the electrically conductive area, to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area; selectively isotropically etching one of the oxide or nitride materials relative to the other of the first and second materials to produce indentations which extend generally laterally into the exposed edges of the multiple layers; providing a layer of conductively doped polysilicon atop the wafer and electrically conductive area to a thickness of from 500 Angstroms to about 1500 Angstroms, and filling the exposed edge indentations with such polysilicon; etching the polysilicon to leave polysilicon extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations; and etching the multiple layers from the wafer to leave upwardly projecting polysilicon having conductive and exposed lateral projections extending therefrom.

Claim 15

A method of fabricating a semiconductor wafer comprising: providing an electrically conductive area on a semiconductor wafer; providing multiple alternating layers of oxide and nitride materials atop the wafer to respective thicknesses of from 200 Angstroms to 1000 Angstroms, the oxide and nitride materials being selectively etchable relative to one another; etching the multiple layers and upwardly exposing the electrically conductive area, to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area; selectively isotropically etching one of the oxide or nitride materials relative to the other of the first and second materials to produce indentations which extend generally laterally into the exposed edges of the multiple layers; providing a layer of conductively doped polysilicon atop the wafer and electrically conductive area to a thickness of from 500 Angstroms to about 1500 Angstroms, and filling the exposed edge indentations with such polysilicon; etching the polysilicon to leave polysilicon extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations; and etching the multiple layers from the wafer to leave upwardly projecting polysilicon having conductive and exposed lateral projections extending therefrom.

Claim 18

A method of fabricating an array of DRAM storage capacitors on a silicon wafer having active areas, word lines and digit lines, the method comprising: applying a dielectric layer atop the wafer; patterning and etching the dielectric layer to upwardly expose selected active area; applying a first electrically conductive layer atop the wafer, the first electrically conductive layer contacting the selected active areas; planarizing the first electrically conductive layer; providing multiple alternating layers of first and second materials atop the wafer over the planarized first electrically conductive layer, the first and second materials being selectively etchable relative to one another; patterning and etching the multiple layers to expose selected portions of the planarized first electrically conductive layer and define exposed edges of the multiple layers which project upwardly from the selected first electrically conductive layer portions; selectively isotropically etching one of the first or second materials relative to the other of the first and second materials to produce indentations which extend generally laterally into the exposed edges of the multiple layers; applying a second layer of electrically conductive material atop the wafer and selected first electrically conductive layer portions, and filling the exposed edge indentations with electrically conductive material; patterning and etching the first and second conductive layers to define individual electrically isolated lower capacitor cell plates having portions which project upwardly adjacent the multiple layer edges and within the indentations; etching the multiple layers from the wafer to leave upwardly projecting conductive material having lateral projections extending therefrom; applying a capacitor dielectric layer atop the wafer over the upwardly projecting conductive material; and applying a third conductive layer atop the wafer over the capacitor dielectric layer to define an upper capacitor plate.

Claim 19

A method of fabricating an array of DRAM storage capacitors on a silicon wafer having active areas, word lines and digit lines, the method comprising: applying a dielectric layer atop the wafer; patterning and etching the dielectric layer to upwardly expose selected active area; applying a first electrically conductive layer atop the wafer, the first electrically conductive layer contacting the selected active areas; planarizing the first electrically conductive layer; providing multiple alternating layers of first and second materials atop the wafer over the planarized first electrically conductive layer, the first and second materials being selectively etchable relative to one another; patterning and etching the multiple layers to expose selected portions of the planarized first electrically conductive layer and define exposed edges of the multiple layers which project upwardly from the selected first electrically conductive layer portions; selectively isotropically etching one of the first or second materials relative to the other of the first and second materials to produce indentations which extend generally laterally into the exposed edges of the multiple layers; applying a second layer of electrically conductive material atop the wafer and selected first electrically conductive layer portions, and filling the exposed edge indentations with electrically conductive material; patterning and etching the first and second conductive layers to define individual electrically isolated lower capacitor cell plates having portions which project upwardly adjacent the multiple layer edges and within the indentations; etching the multiple layers from the wafer to leave upwardly projecting conductive material having lateral projections extending therefrom; applying a capacitor dielectric layer atop the wafer over the upwardly projecting conductive material; and applying a third conductive layer atop the wafer over the capacitor dielectric layer to define an upper capacitor plate.