Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers

Claim 1

A process for creating an N-channel field effect transistor, said transistor having both lightly-doped and heavily-doped source and drain regions and a gate which is superjacent to a pad oxide-insulated monocrystalline silicon substrate, said gate comprising a rectangular solid of conductive material having substantially vertical side walls and a substantially horizontal upper surface, said gate having staircase-profile sidewall spacers fabricated from a pair of TEOS oxide layers, said process comprising the following steps: (a) blanket deposition of a first TEOS oxide layer on top of said gate and on top of said insulated substrate; (b) densification of said first TEOS oxide layer; (c) subjecting said source and drain regions to a low-dosage implant using a first n-type dopant; (d) blanket deposition of a second TEOS oxide layer on top of said first TEOS oxide layer; (e) etching both TEOS oxide layers with a dry anisotropic etch until both TEOS layers have been removed from said horizontal upper surface; (f) subjecting said source and drain regions to a high-dosage implant using a second n-type dopant; and (g) etching the remnant of said second TEOS oxide layer with an isotropic etch until said remnant of said second TEOS layer has been reduced in size to the point where a three step spacer has been created on each side of said gate, the first and third steps of each spacer being comprised of a remnant of said first TEOS layer and the second step of each spacer being comprised of a remnant of s id second TEOS layer.