US4876213A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Salicided source/drain structure
Assignee: Motorola Solutions Inc
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Filing: 1988-10-31
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Granted: 1989-10-24
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Expires: 2008-10-31
Abstract
Abstract A process for fabricating a CMOS device using one sidewall spacer for both the source/drain implant and salicide formation, thereby providing an improved salicided source/drain structure. The use of one sidewall spacer for both the source/drain implant and the silicide formation facilitates the closer spacing of the silicide region to the gate edge. Prior to the salicidation, a silicon overetch is performed to remove the P+ implant in the source/drain and poly regions of the NMOST. The silicon overetch forms a concave surface on the N+ source/drain regions, which allows salicide formation closer to the edge of the channel. Due to the proximity of the edge of the silicide to the edge of the channel, the series resistance of the NMOST is significantly reduced.
Inventors
- 👤 James R. Pfiester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:19
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/608; H10D62/01; H10D62/021; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/021; H10D64/60; H10D64/62; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A process for fabricating a CMOS device comprising the steps of: providing a silicon substrate having first and second surface regions of first and second conductivity type, respectively; providing first and second polycrystalline silicon gate electrodes overlying said first and second surface regions; forming source and drain regions of second and first conductivity type, respectively, self aligned with said first and second gate electrodes; forming sidewall spacers on the edges of each of said gate electrodes; introducing impurities of said first conductivity type into said first and second surface regions using said sidewall spacers as masking elements; removing said impurities of said first conductivity type from said surface region of said first conductivity type by overetching of said substrate surface; selectively introducing impurities of second conductivity type into said surface region of said first conductivity type using said sidewall spacers as masking elements; and forming silicide regions on said first and second surface regions using said sidewall spacers as silicide masks.
Claim 2
Dependent Claim
161 words
A process for fabricating a CMOS device comprising the steps of: providing a silicon substrate having first and second surface regions of first and second conductivity type, respectively; providing first and second polycrystalline silicon gate electrodes overlying said first and second surface regions; forming source and drain regions of second and first conductivity type, respectively, self aligned with said first and second gate electrodes; forming sidewall spacers on the edges of each of said gate electrodes; introducing impurities of said first conductivity type into said first and second surface regions using said sidewall spacers as masking elements; removing said impurities of said first conductivity type from said surface region of said first conductivity type by overetching of said substrate surface; selectively introducing impurities of second conductivity type into said surface region of said first conductivity type using said sidewall spacers as masking elements; and forming silicide regions on said first and second surface regions using said sidewall spacers as silicide masks.
Claim 3
Dependent Claim
37 words
The process of claim 1 wherein a thin dielectric material region is formed over selective areas of said silicon substrate, including said gate electrodes of said first and second regions, by oxidizing said exposed polycrystalline silicon surface.
Claim 4
Dependent Claim
22 words
The process of claim 1 wherein said source and drain regions of first and second conductivity type are formed by ion implantation.
Claim 5
Dependent Claim
56 words
The process of claim 1 wherein said step of forming a silicide region on said first and second surface regions comprises: depositing a refractory metallic material over said first and second surface regions, using said sidewall spacers as silicide masks; annealing said refractory metallic material to form said silicide region said first and second surface regions.
Claim 6
Dependent Claim
11 words
The process of claim 5 wherein the refractory metal comprises titanium.
References Cited (Backward Citations)
US4530150A
Cited
JPS59104167A
Cited
JPS6046071A
Cited
JPS60261171A
Cited
US4599789A
Cited
US4577391A
Cited
US4642878A
Cited
WO1986005321A1
Cited
JPS61214474A
Cited
US4745086A
Cited
US4682404A
Cited
US4753898A
Cited
US4771014A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-23 | 1993-04-24 | 1993-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-23 | 1997-04-24 | 1997-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-23 | 2001-04-24 | 2001-10-24 | $7700.00 | Window Closed / Lapsed |