LDD CMOS process

Claim 2

A process for fabricating a CMOS device comprising the sequential steps of: providing a silicon substrate including surface regions of first and second conductivity type; forming an insulator overlying said surface regions; forming first and second gate electrodes insulatively spaced from said surface regions of first and second conductivity type, respectively depositing a spacer forming material over said first and second electrodes and said surface regions; anisotropically etching said spacer forming material over said surface region of first conductivity type to form spacers at the edges of said first gate electrode while retaining said spacer forming material unetched over said surface region of second conductivity type; implanting conductivity type determining ions of second conductivity type into said surface region of first conductivity type using said spacers as ion implantation masks to thereby form heavily doped regions of second conductivity type in said surface region of first conductivity type; removing said spacers and implanting conductivity determining ions of second conductivity type into said surface region of first conductivity type to thereby form lightly doped regions of second conductivity type at least partially coincident with said heavily doped regions of second conductivity type formed in the previous implantation step; removing said unetched spacer forming material over said surface region of second conductivity type; and performing a blanket implantation of conductivity determining ions of first conductivity type.

Claim 3

The process of claim 1 wherein said spacer forming material comprises polycrystalline silicon.

Claim 4

The process of claim 2 further comprising after said step of depositing a spacer forming material comprising polycrystalline silicon, the step of depositing a barrier material overlying said polycrystalline silicon.

Claim 5

The process of claim 1 further comprising, after said stpe of depositing a spacer forming material, the step of depositing a first barrier layer overlying said spacer forming material.

Claim 6

The process of claim 4 wherein said step of depositing a first barrier layer comprises depositing a layer of silicon nitride.

Claim 7

The process of claim 1 further comprising, after said steps of forming a first gate electrode and a second gate electrode, the step of forming a second barrier layer overlying each of said first and second gate electrodes.

Claim 8

The process of claim 6 wherein said second barrier layer comprises silicon oxide.

Claim 9

The process of claim 1 wherein said insulator comprises silicon oxide.

Claim 10

The process of claim 1 wherein said step of removing said spacer forming material comprises anisotropically etching to form second spacers at the edge of said second gate electrode.

Claim 11

The process of claim 9 wherein said step of implanting conductivity determining ions of first conductivity type further comprises the steps of implanting first conductivity determining ions of first conductivity type using said second spacers as an ion implantation mask; removing said second spacers; and implanting second conductivity determining ions of first conductivity type.

Claim 12

A process for the fabrication of CMOS devices comprising the sequential steps of: providing first and second gate electrodes on a silicon substrate for first and second complementary MOS transistors; forming a first oxide layer and a second spacer material layer overlying said gate electrodes; selectively masking to protect said second layer overlying said second gate electrode; etching exposed portions of said second layer to form first sidewall spacers at edges of said first gate electrode and leaving unetched portions of said second layer overlying said second gate electrode; implanting first conductivity determining impurities of first conductivity type using said first sidewall spacers as an ion implantation mask to thereby form heavily doped regions of first conductivity type in said silicon substrate; removing said first sidewall spacers and implanting conductivity determining impurities of first conductivity type using said first gate electrode as an ion implantation mask; to thereby form lightly doped regions of first conductivity type at least partially coincident with said heavily doped regions of first conductivity type formed in the previous implantation step thermally oxidizing using remaining unetched portions of said second layer as an oxidation mask; etching said remaining unetched portions of said second layer; and performing a blanket implantation of conductivity determining impurities of second conductivity type using said second gate electrode as an ion implantation mask.

Claim 13

A process for the fabrication of CMOS devices comprising the sequential steps of: providing first and second gate electrodes on a silicon substrate for first and second complementary MOS transistors; forming a first oxide layer and a second spacer material layer overlying said gate electrodes; selectively masking to protect said second layer overlying said second gate electrode; etching exposed portions of said second layer to form first sidewall spacers at edges of said first gate electrode and leaving unetched portions of said second layer overlying said second gate electrode; implanting first conductivity determining impurities of first conductivity type using said first sidewall spacers as an ion implantation mask to thereby form heavily doped regions of first conductivity type in said silicon substrate; removing said first sidewall spacers and implanting conductivity determining impurities of first conductivity type using said first gate electrode as an ion implantation mask; to thereby form lightly doped regions of first conductivity type at least partially coincident with said heavily doped regions of first conductivity type formed in the previous implantation step thermally oxidizing using remaining unetched portions of said second layer as an oxidation mask; etching said remaining unetched portions of said second layer; and performing a blanket implantation of conductivity determining impurities of second conductivity type using said second gate electrode as an ion implantation mask.

Claim 14

The process of claim 11 wherein said step of etching said unetched remaining portions comprises etching to form second sidewall spacers at edges of said second gate electrode.

Claim 15

The process of claim 12 further comprising the steps of implanting second conductivity type using said second sidewall spacers as an ion implantation mask; and then removing said sidewall spacers.

Claim 16

A process for fabricating a CMOS device comprising the sequential steps of: providing a silicon substrate including first and second surface regions of first and second conductivity type, respectively, and having an oxide layer on the surface thereof and first and second gate electrodes thereover; forming a first barrier layer overlying said first and second gate electrodes; depositiong a layer of polycrystalline silicon overlying said first barrier layer and exposed poritons of said oxide layer over said first and second regions; forming a second barrier layer overlying said layer of polycrystalline silicon; forming a mask layer overlying said second region; removing exposed portions of said second barrier layer and anisotoropically etching said layer of polycrystalline silicon to leave polycrystalline silicon spacers at the edges of said first gate electrode and unetched portions of said polycrystalline silicon overlying said second region; implanting ions of second conductivity determining type into said first surface region using said spacers as an ion implantation mask to thereby form heavily doped regions of second conductivity type in said surface region of first conductivity type; removing said spacers and implanting ions of second conductivity determining type into said first surface region to thereby form lightly doped regions of second conductivity type at least partially coincident with said heavily doped regions of second conductivity type formed in the previous implantation step; heating in an oxidizing ambient to grow a thermal oxide on said first surface region, said second surface region protected from oxidation by said unetched portions; removing said second barrier layer and said unetched portions of said layer of polycrystalline silicon over said second region; and performer a blanket implantation of ions of first conductivity determining type.

Claim 17

A process for fabricating a CMOS device comprising the sequential steps of: providing a silicon substrate including first and second surface regions of first and second conductivity type, respectively, and having an oxide layer on the surface thereof and first and second gate electrodes thereover; forming a first barrier layer overlying said first and second gate electrodes; depositiong a layer of polycrystalline silicon overlying said first barrier layer and exposed poritons of said oxide layer over said first and second regions; forming a second barrier layer overlying said layer of polycrystalline silicon; forming a mask layer overlying said second region; removing exposed portions of said second barrier layer and anisotoropically etching said layer of polycrystalline silicon to leave polycrystalline silicon spacers at the edges of said first gate electrode and unetched portions of said polycrystalline silicon overlying said second region; implanting ions of second conductivity determining type into said first surface region using said spacers as an ion implantation mask to thereby form heavily doped regions of second conductivity type in said surface region of first conductivity type; removing said spacers and implanting ions of second conductivity determining type into said first surface region to thereby form lightly doped regions of second conductivity type at least partially coincident with said heavily doped regions of second conductivity type formed in the previous implantation step; heating in an oxidizing ambient to grow a thermal oxide on said first surface region, said second surface region protected from oxidation by said unetched portions; removing said second barrier layer and said unetched portions of said layer of polycrystalline silicon over said second region; and performer a blanket implantation of ions of first conductivity determining type.