Mis field effect transistor and manufacture thereof

Abstract

Abstract PURPOSE:To reduce hot carrier effect and to suppress the irregularity of characteristics of an MIS field effect transistor by forming the low density second conductive type impurity layer on a stepwise portion between a lower channel portion of a gate oxidized film and the high density second conductive type impurity-doped layer. CONSTITUTION:A gate Si oxidized film 3 and a polycrystalline Si 4 are formed on a P type Si semiconductor substrate 1, and an impurity such as polycrystalline 4 phosphorus is doped. With a resist pattern 51 as a mask the polycrystalline Si 4 and the film 3 are etched. Arsenic ions are implanted to form N<-> type layers 5, 5'. Further, an etching is performed, and the layers 5, 5' remain on the side wall of the stepwise portion between the gate electrode 4 and the substrate 1. After the resist 51 is removed, arsenic ions are implanted to the entire surface to form N<+> type layers 6, 6', and an annealing is performed. Then, an insulating film 7 is formed, a contacting hole 8 is opened, and aluminum wirings 9 are formed. Evevtually, a protective film 10 is formed of a nitrided Si film.

Inventors

• 👤 Akio Kita
• 👤 北　明夫

Bibliographic Details