Semiconductor memory device and a process for producing the same

Claim 2

A semiconductor integrated circuit device, comprising series circuits including a MISFET and a capacitor, as memory cells, comprising: a semiconductor substrate of a first type of conductivity having a main surface; a first semiconductor region of a second type of conductivity formed in said semiconductor substrate and extending to said main surface, said first semiconductor region serving as one electrode of said capacitor; a second semiconductor region of the first type of conductivity formed under and in contact with said first semiconductor region, said second semiconductor region having an impurity concentration which is higher than the impurity concentration of said semiconductor substrate; and a third semiconductor region, of the first type of conductivity, formed under said second semiconductor region said third semiconductor region having an impurity concentration which is higher than the impurity concentration of said second semiconductor region.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said third semiconductor region is formed so as to extend to a location under said MISFET in said semiconductor substrate.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said MISFET has a source region and a drain region, one of the source and drain regions of said MISFET being electrically connected to said capacitor, and said third semiconductor region is formed so as to extend to a location under said one of the source and drain regions of said MISFET electrically connected to said capacitor.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein the other of the source and drain regions of the MISFET is electronically connected to a data line, and said third semiconductor region does not extend to a location under said other of the source and drain regions.

Claim 6

A semiconductor integrated circuit device according to claim 1, wherein said third semiconductor region has an area which is equal to, or larger than, the area of the second semiconductor region.

Claim 7

A semiconductor integrated circuit device according to claim 1, wherein the second and third semiconductor regions have impurity concentration distribution having a peak impurity concentration at a second depth and a third depth, respectively, from the main surface of the semiconductor substrate; wherein the first semiconductor region extends to a first depth from the main surface of the semiconductor substrate; and wherein either the second depth or the third depth is deeper than said first depth.

Claim 8

A semiconductor integrated circuit device, having a memory array including a plurality of memory cells arranged in first and second directions, each of said memory cells being comprised of a series circuit of a MISFET and a capacitor, said semiconductor integrated circuit device comprising: a semiconductor substrate of a first type of conductivity having a main surface; a first semiconductor region of a second type of conductivity formed in said semiconductor substrate and extending to said main surface, said first semiconductor region serving as one electrode of said capacitor; a second semiconductor region of the first type of conductivity which is formed under said first semiconductor region and in a portion between said first semiconductor regions neighboring in said first direction, said second semiconductor region having an impurity concentration higher than the impurity concentration of said semiconductor substrate; and a third semiconductor region of the first type of conductivity which is formed at least under said second semiconductor region, said third semiconductor region having an impurity concentration higher than the impurity concentration of said second semiconductor region.

Claim 9

A semiconductor integrated circuit device, having a memory array including a plurality of memory cells arranged in first and second directions, each of said memory cells being comprised of a series circuit of a MISFET and a capacitor, said semiconductor integrated circuit device comprising: a semiconductor substrate of a first type of conductivity having a main surface; a first semiconductor region of a second type of conductivity formed in said semiconductor substrate and extending to said main surface, said first semiconductor region serving as one electrode of said capacitor; a second semiconductor region of the first type of conductivity which is formed under said first semiconductor region and in a portion between said first semiconductor regions neighboring in said first direction, said second semiconductor region having an impurity concentration higher than the impurity concentration of said semiconductor substrate; and a third semiconductor region of the first type of conductivity which is formed at least under said second semiconductor region, said third semiconductor region having an impurity concentration higher than the impurity concentration of said second semiconductor region.

Claim 10

A semiconductor integrated circuit device according to claim 7, wherein said third semiconductor region is formed to extend the whole area of said memory array.

Claim 11

A semiconductor integrated circuit device according to claim 7, wherein said third semiconductor region is formed under said MISFET except under the regions that serve as a source region or drain region of said MISFET and that area connected to data lines.

Claim 12

A semiconductor integrated circuit device according to claim 7, wherein the second and third semiconductor regions have impurity concentration distributions having a peak impurity concentration at a second depth and a third depth, respectively, from the main surface of the semiconductor substrate; wherein the first semiconductor region extends to a first depth from the main surface of the semiconductor substrate; and wherein either the second depth or the third depth is deeper than said first depth.

Claim 13

A semiconductor integrated circuit device according to claim 7, wherein the third semiconductor region is in contact with the second semiconductor region.

Claim 14

A semiconductor integrated circuit device according to claim 7, wherein the third semiconductor region is spaced from the second semiconductor region.

Claim 15

A semiconductor integrated circuit device according to claim 3, further comprising: a conductive film positioned over said main surface of said semiconductor substrate at the portion over said first semiconductor region, as another electrode of said capacitor.

Claim 16

A semiconductor integrated circuit device according to claim 13, wherein said conductive film is comprised of a polycrystalline silicon film.

Claim 17

A semiconductor integrated circuit device having a plurality of series circuits each having a MISFET and a capacity, arranged in first and second directions, as memory cells, comprising: a semiconductor substrate of a first type of conductivity having a main surface; two first semiconductor regions of a second type of conductivity formed in said semiconductor substrate spaced from each other and each extending to said main surface, each of said first semiconductor regions serving as one electrode of a respective one of the capacitors; a second semiconductor region of the first type of conductivity formed under and in contact with said first semiconductor regions, said second semiconductor region having an impurity concentration which is higher than the impurity concentration of said semiconductor substrate; a third semiconductor region, of the first type of conductivity, formed under said second semiconductor region, said third semiconductor region having an impurity concentration which is higher than the impurity concentration of said second semiconductor region; and a first insulating film over said main surface of said semiconductor substrate at a portion between said two first semiconductor regions.

Claim 18

A semiconductor integrated circuit device having a plurality of series circuits each having a MISFET and a capacity, arranged in first and second directions, as memory cells, comprising: a semiconductor substrate of a first type of conductivity having a main surface; two first semiconductor regions of a second type of conductivity formed in said semiconductor substrate spaced from each other and each extending to said main surface, each of said first semiconductor regions serving as one electrode of a respective one of the capacitors; a second semiconductor region of the first type of conductivity formed under and in contact with said first semiconductor regions, said second semiconductor region having an impurity concentration which is higher than the impurity concentration of said semiconductor substrate; a third semiconductor region, of the first type of conductivity, formed under said second semiconductor region, said third semiconductor region having an impurity concentration which is higher than the impurity concentration of said second semiconductor region; and a first insulating film over said main surface of said semiconductor substrate at a portion between said two first semiconductor regions.

Claim 19

A semiconductor integrated circuit device according to claim 15, wherein each said MISFET has a source region and a drain region, one of the source and drain regions of said MISFET being electrically connected to said capacitor, and said third semiconductor region is formed so as to extend to a location under said one of the source and drain regions of said MISFET electrically connected to said capacitor.

Claim 20

A semiconductor integrated circuit device according to claim 16, wherein the second and third semiconductor regions have impurity concentration distribution having a peak impurity concentration at a second depth and a third depth, respectively, from the main surface of the semiconductor substrate; wherein the first semiconductor region extends to a first depth from the main surface of the semiconductor substrate; and wherein either the second depth or the third depth is deeper than said first depth.

Claim 21

A semiconductor integrated circuit device according to claim 15, further comprising: a second insulating film positioned on said main surface of said semiconductor substrate at a position over said first semiconductor regions.

Claim 22

A semiconductor integrated circuit device according to claim 18, wherein said second insulating film is comprised of a silicon oxide film.

Claim 23

A semiconductor integrated circuit device according to claim 18, further comprising: a conductive film positioned on said second insulating film, as another electrode of said capacitors.

Claim 24

A semiconductor integrated circuit device according to claim 20, wherein said conductive film is comprised of a polycrystalline silicon film.

Claim 25

A semiconductor integrated circuit device according to claim 16, wherein a gate electrode of said MISFET is comprised of a silicide film or stacked film of a polycrystalline silicon layer and a silicide layer thereon.

Claim 26

A semiconductor integrated circuit device according to claim 22, wherein said gate electrode of said MISFET constitutes a word line extending in said first direction.

Claim 27

A semiconductor integrated circuit device according to claim 21, wherein another of the source and drain regions of the MISFET is electrically connected to a data line extending in said second direction.

Claim 28

A semiconductor integrated circuit device according to claim 13, further comprising: a first insulating film positioned on said main surface of said semiconductor substrate at the portion over the first semiconductor region.

Claim 29

A semiconductor integrated circuit device according to claim 25, wherein said first insulating film is comprised of silicon oxide.