Dynamic memory cell and method for manufacturing the same

Claim 1

A dynamic memory device comprising: a plurality of dynamic memory cells arranged in a matrix of rows and columns; each memory cell having: a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate, at least one hole formed in said semiconductor layer, said semiconductor layer having an impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed on the inner surface of the hole in the first semiconductor layer, an insulating layer formed on the second semiconductor layer for forming a capacitor and a conductive layer formed on the inner surface of the insulating layer; a third semiconductor layer of the first conductivity type formed in the surface area of the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer; a MOS (metal oxide semiconductor) transistor formed in the third semiconductor layer; and means for electrically separating said memory cell from at least one of the adjacent dynamic memory cells in the column direction and adjacent memory cells in the row direction, comprised of an extended area of the first semiconductor layer which extends between the dynamic memory cell and the adjacent dynamic memory cell, and an insulating film which is formed on the extended area of the first semiconductor layer, said insulating film having a thickness equal to, or smaller than, that of the insulating layer used in forming the capacitor.