US4538166A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-01-17
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Granted: 1985-08-27
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Expires: 2004-01-17
Abstract
Abstract A 1-transistor and 1-capacitor type memory cell includes a first capacitor electrode and a field shield electrode which serves as the second capacitor electrode of the memory cell. A high impurity concentration layer is formed just beneath the first electrode of the capacitor of the memory cell and extends to a field region to form a channel stop area. However, the high impurity concentration layer is inhibited from extending to the transistor gate. This arrangement provides so-called 1-transistor and 1-capacitor type memory cells which are highly integrated, have a long persisting time and are resistant to alpha rays.
Inventors
- 👤 Motoo Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:03
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
329 words
A semiconductor memory device including a plurality of memory cells, each of which comprises a transistor and a capacitor, said memory device comprising: a semiconductor substrate of a first conductivity type; an insulator layer formed on the surface of said semiconductor substrate; a first semiconductor region of a second conductivity type, opposite said first conductivity type, formed in said semiconductor substrate beneath said insulator layer, said first semiconductor region functioning as one electrode of the capacitor of a memory cell; a second semiconductor region of the first conductivity type having a first portion formed in said semiconductor substrate beneath said first semiconductor region, and having a second portion formed in said semiconductor substrate in a field area surrounding said first semiconductor region, each of said first and second portions having an impurity concentration higher than that of said semiconductor substrate, said first and second portions having different thicknesses; a conductive layer formed on the portion of said insulator layer covering said first and second semiconductor regions and serving as the other electrode of the capacitor and as a field shield electrode, said conductive layer having a pattern identical to that of said second semiconductor region except at the portion where the capacitor is coupled to the transistor by said first semiconductor region; and a gate conductor formed on said insulator layer and spaced apart from said conductive layer, said gate conductor functioning as a gate of the transistor of the memory cell; said first semiconductor region having first and second portions, the first portion of said second semiconductor region being located beneath the first portion of said first semiconductor region, the second portion of said first semiconductor region being located under an area between said conductive layer and said gate conductor so as to connect the first portion of said first semiconductor region to the transistor, the second portion of said first semiconductor region having a depth greater than that of the first portion of said first semiconductor region.
Claim 2
Dependent Claim
329 words
A semiconductor memory device including a plurality of memory cells, each of which comprises a transistor and a capacitor, said memory device comprising: a semiconductor substrate of a first conductivity type; an insulator layer formed on the surface of said semiconductor substrate; a first semiconductor region of a second conductivity type, opposite said first conductivity type, formed in said semiconductor substrate beneath said insulator layer, said first semiconductor region functioning as one electrode of the capacitor of a memory cell; a second semiconductor region of the first conductivity type having a first portion formed in said semiconductor substrate beneath said first semiconductor region, and having a second portion formed in said semiconductor substrate in a field area surrounding said first semiconductor region, each of said first and second portions having an impurity concentration higher than that of said semiconductor substrate, said first and second portions having different thicknesses; a conductive layer formed on the portion of said insulator layer covering said first and second semiconductor regions and serving as the other electrode of the capacitor and as a field shield electrode, said conductive layer having a pattern identical to that of said second semiconductor region except at the portion where the capacitor is coupled to the transistor by said first semiconductor region; and a gate conductor formed on said insulator layer and spaced apart from said conductive layer, said gate conductor functioning as a gate of the transistor of the memory cell; said first semiconductor region having first and second portions, the first portion of said second semiconductor region being located beneath the first portion of said first semiconductor region, the second portion of said first semiconductor region being located under an area between said conductive layer and said gate conductor so as to connect the first portion of said first semiconductor region to the transistor, the second portion of said first semiconductor region having a depth greater than that of the first portion of said first semiconductor region.
Claim 3
Dependent Claim
308 words
A semiconductor memory device including a plurality of memory cells, each of which comprises a transistor and a capacitor, said memory device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type opposite said first conductivity type, formed in said semiconductor substrate, said first semiconductor region including an electrode portion, functioning as a first electrode of the capacitor of a memory cell, and a coupling portion for coupling the capacitor to the transistor, the coupling portion having a depth greater than that of the electrode portion; a second semiconductor region of the first conductivity type having a first portion formed in said semiconductor substrate beneath the electrode portion of said first semiconductor region and having a second portion formed in said semiconductor substrate in a field area surrounding said first semiconductor region, said first and second portions having first and second impurity concentrations, respectively, both of which are higher than that of said semiconductor substrate, said first and second portions having first and second thicknesses, respectively; an insulator layer formed on the surface of said semiconductor substrate; a conductive layer formed on said insulator layer, said conductive layer serving as the second electrode of the capacitor and as a field shield electrode, said conductive layer having a pattern identical to that of said second semiconductor region except at the portion of said second semiconductor region underlying the coupling portion of said first semiconductor region; and a gate conductor formed on said insulator layer and spaced apart from said conductive layer, said gate conductor functioning as a gate of the transistor of the memory cell, the coupling portion of said first semiconductor region being located under an area between said conductive layer and said gate conductor so as to connect the electrode portion of said first semiconductor region to the transistor.
Claim 4
Dependent Claim
308 words
A semiconductor memory device including a plurality of memory cells, each of which comprises a transistor and a capacitor, said memory device comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type opposite said first conductivity type, formed in said semiconductor substrate, said first semiconductor region including an electrode portion, functioning as a first electrode of the capacitor of a memory cell, and a coupling portion for coupling the capacitor to the transistor, the coupling portion having a depth greater than that of the electrode portion; a second semiconductor region of the first conductivity type having a first portion formed in said semiconductor substrate beneath the electrode portion of said first semiconductor region and having a second portion formed in said semiconductor substrate in a field area surrounding said first semiconductor region, said first and second portions having first and second impurity concentrations, respectively, both of which are higher than that of said semiconductor substrate, said first and second portions having first and second thicknesses, respectively; an insulator layer formed on the surface of said semiconductor substrate; a conductive layer formed on said insulator layer, said conductive layer serving as the second electrode of the capacitor and as a field shield electrode, said conductive layer having a pattern identical to that of said second semiconductor region except at the portion of said second semiconductor region underlying the coupling portion of said first semiconductor region; and a gate conductor formed on said insulator layer and spaced apart from said conductive layer, said gate conductor functioning as a gate of the transistor of the memory cell, the coupling portion of said first semiconductor region being located under an area between said conductive layer and said gate conductor so as to connect the electrode portion of said first semiconductor region to the transistor.
Claim 5
Dependent Claim
17 words
A semiconductor memory device as set forth in claim 2, wherein said first conductivity type is p-type.
Claim 6
Dependent Claim
17 words
A semiconductor memory device as set forth in claim 2, wherein said conductive layer is polycrystal silicon.
Claim 7
Dependent Claim
17 words
A semiconductor memory device as set forth in claim 4, wherein said insulator layer comprises silicon dioxide.
Claim 8
Dependent Claim
24 words
A semiconductor memory device as set forth in claim 4, wherein said insulator layer comprises a silicon dioxide layer and a silicon nitride layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-26 | 1989-02-25 | 1989-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-26 | 1993-02-25 | 1993-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-26 | 1997-02-25 | 1997-08-27 | $7700.00 | Window Closed / Lapsed |