Field effect transistors and fabrication of integrated circuits containing the transistors

Claim 1

A field effect transistor (FET) which comprises: (A) semiconductive substrate of a first conductive type containing active impurities of a first conductive type; (b) FET channel region containing active impurities of said first conductive type; (C) FET gate insulator over the channel region; (D) doped polycrystalline silicon gate over said channel region and said FET gate insulator; wherein the boundaries of said polycrystalline silicon gate determine the boundaries of said channel region in both the width and length directions; (E) doped source region of second and opposite conductive type; said source region being self-aligned with respect to one end of the FET gate in the length direction; (F) doped drain region of a second and opposite conductive type; said drain region being self-aligned with respect to the other end of the FET gate in the length direction; (G) field oxide to isolate said FET from other like FETs and from other structures and circuits on the same semiconductive substrate; (H) said field oxide being nonrecessed with respect to the source and drain regions; (I) said field oxide isolation being self-aligned with respect to the sides of the FET gate in the width direction, and said gate neither overlapping nor underlapping said field oxide isolation; (J) insulation layer at least over the FET source, and FET drain, but not over the FET gate; (K) a metallic-type high electrical conductivity interconnection line; (L) a self-registering electrical connection between the polycrystalline silicon gate and said interconnection line; (M) contact holes to provide vias for achieving electrical connection to FET source and drain regions; (N) metallic-type high electrical conductivity interconnection lines making electrical connection to said FET source and drain regions through said vias; and (O) electrical connections to said semiconductive substrate.