US4262298A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ram having a stabilized substrate bias and low-threshold narrow-width transfer gates
Assignee: Samsung Electronics Co Ltd
•
Filing: 1979-09-04
•
Granted: 1981-04-14
•
Expires: 1999-09-04
Abstract
Abstract Disclosed is a RAM that includes a semiconductor substrate having P-type dopant impurity atoms and having a major surface. A plurality of spaced apart regions of N-type atoms lie within a predetermined area on the surface to define storage regions for the cells of the memory. An insulating layer of substantially uniform thickness with a conductive layer lying thereon completely covers the predetermined area except for a plurality of elongated openings which extend outward from each of the storage regions. A layer of P-type dopant atoms lie at substantially the same level as the storage regions throughout that portion of the substrate that is beneath the insulating layer. By this structure, the perimeter of a transfer gate that exhibits essentially no narrow channel width effect is defined from each storage region by the respective openings. Also, a capacitor for stabilizing the bias voltage of the substrate is formed by the combination of that portion of the insulating layer and conductive layer which lies between the storage regions.
Inventors
- 👤 Hsing T. Tuan
- 👤 Donald L. Henderson, Sr.
- 👤 Robert N. Ruth, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:44
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/4076; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
186 words
A semiconductor memory comprised of: a semiconductor substrate having dopant impurity atoms of a first type and having a major surface; a plurality of spaced apart regions of dopant atoms of a second type opposite to said first type lying within a predetermined area on said surface defining storage regions for the cells of said memory; an insulating layer of substantially uniform thickness with a conductive layer lying thereon completely covering said predetermined area except for a plurality of elongated openings which extend outward from each of said storage regions; and a layer of dopant impurity atoms of said first type at substantially the same level as said storage regions throughout that portion of said substrate that lies beneath said conductive layer superimposed on said substrate doping; whereby the perimeter of a transfer channel having substantially no narrow channel width effect is defined from each storage region by said openings, and whereby a capacitor for stabilizing the voltage between said substrate and said conductive layer is formed by the combination of that portion of said insulating layer and conductive layer which lies between said storage regions.
Claim 2
Dependent Claim
186 words
A semiconductor memory comprised of: a semiconductor substrate having dopant impurity atoms of a first type and having a major surface; a plurality of spaced apart regions of dopant atoms of a second type opposite to said first type lying within a predetermined area on said surface defining storage regions for the cells of said memory; an insulating layer of substantially uniform thickness with a conductive layer lying thereon completely covering said predetermined area except for a plurality of elongated openings which extend outward from each of said storage regions; and a layer of dopant impurity atoms of said first type at substantially the same level as said storage regions throughout that portion of said substrate that lies beneath said conductive layer superimposed on said substrate doping; whereby the perimeter of a transfer channel having substantially no narrow channel width effect is defined from each storage region by said openings, and whereby a capacitor for stabilizing the voltage between said substrate and said conductive layer is formed by the combination of that portion of said insulating layer and conductive layer which lies between said storage regions.
Claim 3
Dependent Claim
25 words
A semiconductor memory according to claim 1 wherein said first type dopant impurity atoms are P-type and said second type dopant impurity atoms are N-type.
Claim 4
Dependent Claim
25 words
A semiconductor memory according to claim 1 wherein said first type dopant impurity atoms are N-type and said second type dopant impurity atoms are P-type.
Claim 5
Dependent Claim
25 words
A semiconductor memory according to claim 1 wherein said insulating layer consists of SiO 2 , and said conductive layer consists of heavily doped polysilicon.
Claim 6
Dependent Claim
45 words
A semiconductor memory according to claim 1 wherein said layer of dopant atoms of said first type does not extend into said substrate beneath said openings, but lying therein in a separate layer of dopant atoms of said first type with a lower concentration density.
Claim 7
Dependent Claim
45 words
A semiconductor memory according to claim 1 wherein said layer of dopant atoms of said first type extends throughout said substrate beneath said openings, and also superimposed thereon is a separate layer of dopant atoms of said second type but of a lower concentration density.
Claim 8
Dependent Claim
35 words
A semiconductor memory according to claim 1 wherein said openings extend outward from said storage regions to define the perimeter of transfer gate regions and adjacent buried contact regions on the surface of said substrate.
Claim 9
Dependent Claim
35 words
A semiconductor memory according to claim 1 wherein said openings extend outward from said storage regions to define the perimeter of transfer gate regions and adjacent bit line regions on the surface of said substrate.
Claim 10
Dependent Claim
181 words
A semiconductor memory comprised of: a semiconductor substrate having dopant impurity atoms of a first type and having a major surface; a plurality of relatively shallow spaced apart regions of dopant atoms of a second type opposite to said first type lying within a predetermined area on said surface defining storage regions for the cells of said memory; an insulating layer of substantially unifrom thickness with a conductive layer lying thereon completely covering said predetermined area except for a plurality of elongated openings which extend outward from each of said storage regions; and a relatively deep layer of dopant impurity atoms of said first type throughout that portion of said substrate that lies beneath said conductive layer superimposed on said substrate doping; whereby the perimeter of a transfer channel having substantially no narrow channel width effect is defined from each storage region by said openings, and whereby a capacitor for stabilizing the voltage between said substrate and said conductive layer is formed by the combination of that portion of said insulating layer and conductive layer which lies between said storage regions.
Claim 11
Dependent Claim
181 words
A semiconductor memory comprised of: a semiconductor substrate having dopant impurity atoms of a first type and having a major surface; a plurality of relatively shallow spaced apart regions of dopant atoms of a second type opposite to said first type lying within a predetermined area on said surface defining storage regions for the cells of said memory; an insulating layer of substantially unifrom thickness with a conductive layer lying thereon completely covering said predetermined area except for a plurality of elongated openings which extend outward from each of said storage regions; and a relatively deep layer of dopant impurity atoms of said first type throughout that portion of said substrate that lies beneath said conductive layer superimposed on said substrate doping; whereby the perimeter of a transfer channel having substantially no narrow channel width effect is defined from each storage region by said openings, and whereby a capacitor for stabilizing the voltage between said substrate and said conductive layer is formed by the combination of that portion of said insulating layer and conductive layer which lies between said storage regions.
Claim 12
Dependent Claim
25 words
A semiconductor memory according to claim 9 wherein said first type dopant impurity atoms are P-type and said second type dopant impurity atoms are N-type.
Claim 13
Dependent Claim
25 words
A semiconductor memory according to claim 9 wherein said first type dopant impurity atoms are N-type and said second type dopant impurity atoms are P-type.
Claim 14
Dependent Claim
25 words
A semiconductor memory according to claim 9 wherein said insulating layer consists of SiO 2 , and said conductive layer consists of heavily doped polysilicon.
Claim 15
Dependent Claim
45 words
A semiconductor memory according to claim 9 wherein said layer of dopant atoms of said first type does not extend into said substrate beneath said openings, but lying therein is a separate layer of dopant atoms of said first type with a lower concentration density.
Claim 16
Dependent Claim
45 words
A semiconductor memory according to claim 9 wherein said layer of dopant atoms of said first type extends throughout said substrate beneath said openings, and also superimposed thereon is a separate layer of dopant atoms of said second type but of a lower concentration density.
Claim 17
Dependent Claim
35 words
A semiconductor memory according to claim 9 wherein said openings extend outward from said storage regions to define the perimeter of transfer gate regions and adjacent buried contact regions on the surface of said substrate.
Claim 18
Dependent Claim
35 words
A semiconductor memory according to claim 9 wherein said openings extend outward from said storage regions to define the perimeter of transfer gate regions and adjacent bit line regions on the surface of said substrate.
Claim 19
Dependent Claim
125 words
A memory cell comprised of: a semiconductor substrate having dopant atoms of a first type and having a major surface; a region of dopant atoms of a second type opposite to said first type lying in said surface defining the storage region for said cell; an insulating layer of substantially uniform thickness with a conductive layer lying thereon covering a predetermined area of said surface that includes and extends laterally from said storage region except for an elongated opening which extends outward from said storage region; and a layer of dopant atoms of said first type throughout that portion of said substrate that lies beneath said conductive layer at substantially the same depth as said region of second type atoms superimposed on said substrate doping.
Claim 20
Dependent Claim
125 words
A memory cell comprised of: a semiconductor substrate having dopant atoms of a first type and having a major surface; a region of dopant atoms of a second type opposite to said first type lying in said surface defining the storage region for said cell; an insulating layer of substantially uniform thickness with a conductive layer lying thereon covering a predetermined area of said surface that includes and extends laterally from said storage region except for an elongated opening which extends outward from said storage region; and a layer of dopant atoms of said first type throughout that portion of said substrate that lies beneath said conductive layer at substantially the same depth as said region of second type atoms superimposed on said substrate doping.
Claim 21
Dependent Claim
117 words
A memory cell comprised of: a semiconductor substrate having dopant atoms of a first type and having a major surface; a relatively shallow region of dopant atoms of a second type opposite to said first type lying in said surface defining the storage region for said cell; an insulating layer of substantially uniform thickness with a conductive layer laying thereon covering a predetermined area of said surface that includes and extends laterally from said storage region except for an elongated opening which extends outward from said storage region; and a relatively deep layer of dopant atoms of said first type throughout that portion of said substrate that lies beneath said conductive layer superimposed on said substrate doping.
Claim 22
Dependent Claim
117 words
A memory cell comprised of: a semiconductor substrate having dopant atoms of a first type and having a major surface; a relatively shallow region of dopant atoms of a second type opposite to said first type lying in said surface defining the storage region for said cell; an insulating layer of substantially uniform thickness with a conductive layer laying thereon covering a predetermined area of said surface that includes and extends laterally from said storage region except for an elongated opening which extends outward from said storage region; and a relatively deep layer of dopant atoms of said first type throughout that portion of said substrate that lies beneath said conductive layer superimposed on said substrate doping.
Claim 23
Dependent Claim
105 words
An integrated circuit comprised of: a semiconductor substrate having dopant atoms of a first type and having a major surface; an insulating layer of substantially uniform thickness with a conductive layer lying thereon covering a predetermined area of said surface except for an opening within said area defining the perimeter of an active device; and a layer of dopant atoms of said first type throughout that portion of said substrate surface that lies beneath said conductive layer superimposed on said substrate doping; whereby said insulating layer, conductive layer, and layer of dopant atoms form a capacitor to stabilize the substrate voltage of said active device.
Claim 24
Dependent Claim
105 words
An integrated circuit comprised of: a semiconductor substrate having dopant atoms of a first type and having a major surface; an insulating layer of substantially uniform thickness with a conductive layer lying thereon covering a predetermined area of said surface except for an opening within said area defining the perimeter of an active device; and a layer of dopant atoms of said first type throughout that portion of said substrate surface that lies beneath said conductive layer superimposed on said substrate doping; whereby said insulating layer, conductive layer, and layer of dopant atoms form a capacitor to stabilize the substrate voltage of said active device.
Claim 25
Dependent Claim
44 words
An integrated circuit according to claim 19 wherein said opening is rectangular with a predetermined length/width ratio, and wherein said circuit further includes a conductive gate lying transverse to said opening on an insulating layer to define a MOS transistor as said active device.
References Cited (Backward Citations)
US4183040A
Cited
US4141027A
Cited
US4184085A
Cited
US4158238A
Cited
US4145233A
Cited
US4203125A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-04-13 | 1984-10-13 | 1985-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-04-13 | 1988-10-13 | 1989-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-04-13 | 1992-10-13 | 1993-04-14 | $7700.00 | Window Closed / Lapsed |