EP0085988A2
Expired / Lapsed
EP
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Semiconductor memory and method for fabricating the same
Assignee: Hitachi Ltd
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Filing: 1983-02-09
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Granted: —
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Expires: 2003-02-09
Abstract
Abstract A semiconductor memory having a capacitor (1) formed by utilizing a groove (17) formed in a semiconductor substrate (10) and an insulated gate field effect transistor (2) and suppressing expansion of a depletion layer (201, 202) from the groove, and a method for fabricating the same are disclosed. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high density integration is facilitated.
Inventors
- 👤 Hideo Sunami
- 👤 Tokuo Kure
- 👤 Yoshifumi Kawamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 15:12
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
87 words
A semiconductor memory comprising: a capacitor (1) for storing information; an insulated gate field effect transistor (2) connected to the capacitor (1) for writing and reading charge in and from said capacitor, said capacitor having an electrode (8) formed on a wall of a- groove (17)-formed in a semiconductor substrate (10) with an insulation film (12) being interleaved between the wall and the electrode; said semiconductor substrate including therein means (22, 23, 25, 28) for suppressing expansion of a depletion layer (201, 202) growing around said groove.
Claim 2
Dependent Claim
87 words
A semiconductor memory comprising: a capacitor (1) for storing information; an insulated gate field effect transistor (2) connected to the capacitor (1) for writing and reading charge in and from said capacitor, said capacitor having an electrode (8) formed on a wall of a- groove (17)-formed in a semiconductor substrate (10) with an insulation film (12) being interleaved between the wall and the electrode; said semiconductor substrate including therein means (22, 23, 25, 28) for suppressing expansion of a depletion layer (201, 202) growing around said groove.
Claim 3
Dependent Claim
53 words
A semiconductor memory according to Claim 1 wherein said means for suppressing the expansion of said depletion layer is a highly doped impurity region (22, 23, 28) of the same conductivity as said semiconductor substrate, said highly doped impurity region (22; 23, 28) having a carrier concentration higher than that of said substrate.
Claim 4
Dependent Claim
34 words
A semiconductor memory according to Claim 2 wherein at least one memory cell having said capacitor (1) and said insulated gate field effect transistor (2) is formed in said highly doped impurity region (22).
Claim 5
Dependent Claim
27 words
A semiconductor memory according to Claim 3 wherein a memory mat containing a plurality of said memory cells is formed in said highly doped impurity region (22).
Claim 6
Dependent Claim
37 words
A semiconductor memory according to Claim 3 wherein the insulation film (12) of said capacitor is deposited on said groove (17) and the electrode (8) of said capacitor (1) includes a plate electrode of a conductive material.
Claim 7
Dependent Claim
67 words
A semiconductor memory according to Claim 3, wherein said capacitor has another capacitor electrode including another highly doped impurity layer (24) having the opposite conductivity type to said semiconductor substrate (10), formed in a surface area of said groove (17) adjacent to the surface of said groove, the insulation layer (12) deposited on said groove and the electrode (8) including a plate electrode of a conductive material.
Claim 8
Dependent Claim
16 words
A semiconductor memory according to Claim 5 wherein said highly doped impurity region is of p-type.
Claim 9
Dependent Claim
25 words
A semiconductor memory according to Claim 6 wherein said semiconductor substrate is of p-type and said another highly doped impurity layer (24) is of n-type.
Claim 10
Dependent Claim
21 words
A semiconductor memory according to Claim 7 or 8 wherein said plate electrode (8) is made chiefly of highly doped poly-silicon.
Claim 11
Dependent Claim
32 words
A semiconductor memory according to Claim 2 wherein said highly doped impurity region (22, 23, 28) is formed in the surface area of said groove (17) along the surface of said groove.
Claim 12
Dependent Claim
31 words
A semiconductor memory according-to Claim 10 wherein said capacitor has the insulation film (12) deposited on said groove (17) and the electrode including a plate electrode (8) of a conductive material.
Claim 13
Dependent Claim
49 words
A semiconductor memory according to Claim 10 wherein the capacitor further includes another capacitor electrode of another highly doped impurity layer (24) having the opposite conductivity type to said highly doped impurity region (22, 23, 28) formed in said highly doped region adjacent to the surface of said groove.
Claim 14
Dependent Claim
27 words
A semiconductor memory according to Claim 1 wherein said means for suppressing the expansion of said depletion layer is a groove (25) formed in said semiconductor substrate.
Claim 15
Dependent Claim
29 words
A semiconductor memory according to Claim 13 wherein an insulation film (27) is deposited on the surface of said groove (25) and said groove is filled with poly-silicon (26).
Claim 16
Independent Claim
99 words
A method for fabricating a semiconductor memory comprising the steps of: . (1) forming an insulation film (11, 111) on a semiconductor substrate (10); (2) forming a groove (17) at a selected area of said semiconductor substrate (10) through said insulation film (11, 111); (3) introducing an impurity through the surface of said groove (17) to form a highly doped impurity layer (28) in a surface area of said groove (17) along the surface of said groove; and (4) depositing an insulation film (18, 19) and a conductive film (8) in stack on the surface of said groove (17).
Claim 17
Independent Claim
99 words
A method for fabricating a semiconductor memory comprising the steps of: . (1) forming an insulation film (11, 111) on a semiconductor substrate (10); (2) forming a groove (17) at a selected area of said semiconductor substrate (10) through said insulation film (11, 111); (3) introducing an impurity through the surface of said groove (17) to form a highly doped impurity layer (28) in a surface area of said groove (17) along the surface of said groove; and (4) depositing an insulation film (18, 19) and a conductive film (8) in stack on the surface of said groove (17).
Claim 18
Dependent Claim
29 words
A method for fabricating a semiconductor memory according to Claim 15 wherein said impurity layer in said step (3) has the same conductivity type as said semiconductor substrate (10).
Claim 19
Dependent Claim
26 words
A method for fabricating a semiconductor memory according to Claim 15 or 16 wherein said conductive film in said step (4) is chiefly made of poly-silicon.
Claim 20
Dependent Claim
46 words
A method for fabricating a semiconductor memory according to Claim 15 wherein an impurity having the opposite conductivity type to said semiconductor substrate is introduced into the surface area (29) of said semiconductor substrate prior to the formation of said insulation film in said step (1).
Claim 21
Dependent Claim
28 words
A method for fabricating a semiconductor memory according to Claim 18 wherein said step (3) further includes doping impurity of the opposite conductivity type to said semiconductor substrate.
Claim 22
Dependent Claim
94 words
A method for fabricating a semiconductor memory according to Claim 18 wherein said step (3) includes; introducing an impurity having the same conductivity type as said semiconductor substrate through the surface of said groove to form a highly doped impurity layer in a surface area of said groove and then introducing an impurity of the opposite conductivity type to said semiconductor substrate through the exposed areas of said groove and said semiconductor substrate to form a highly doped impurity layer extending from the surface of said groove to the surface of said semiconductor substrate.
References Cited (Backward Citations)
No citation records indexed.
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