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US4821085A Expired / Lapsed US ⏱️ 0.0 years remaining

VLSI local interconnect structure

Assignee: Texas Instruments Inc
•
Filing: 1985-05-01
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Granted: 1989-04-11
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Expires: 2005-05-01
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Abstract

Abstract A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. However, the present invention patterns this conductive layer, thereby providing a local interconnect with the sheet resistance of the order of one ohm per square. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect level fulfills all of the functions which a buried contact layer could fulfill, and fulfills other functions as well.

Inventors

  • 👤 Roger A. Haken
  • 👤 Thomas C. Holloway

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 11:48
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B41/00; H10B41/40; H10B10/00; H10B10/12; H10B10/125; H10B12/30; H10B12/31; H10B41/42; H10B41/43; H10B41/48; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/682; H10D1/684; H10D1/692; H10D1/696; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/416; H10P14/60; H10P14/63; H10P14/6302; H10P14/6316; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698; H10D84/8312; Y; Y10; Y10S; Y10S257/00; Y10S257/915

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 84 words
An integrated circuit comprising: a substrate having a silicon upper portion; device isolation regions defining predetermined active device areas; a plurality of active devices in said active device areas, portions of said active devices being formed from a conductive first thin film layer; a local interconnect layer distinct from said first thin film layer, said local interconnect layer comprising lines predominantly comprising titanium nitride, said lines of said local interconnect layer interconnecting predetermined portions of said active device regions over said device isolation regions.
Claim 2
Dependent Claim 84 words
An integrated circuit comprising: a substrate having a silicon upper portion; device isolation regions defining predetermined active device areas; a plurality of active devices in said active device areas, portions of said active devices being formed from a conductive first thin film layer; a local interconnect layer distinct from said first thin film layer, said local interconnect layer comprising lines predominantly comprising titanium nitride, said lines of said local interconnect layer interconnecting predetermined portions of said active device regions over said device isolation regions.
Claim 3
Dependent Claim 17 words
The device of claim 2, wherein said titanium nitride interconnect lines are less than 2000 angstroms thick.
Claim 4
Dependent Claim 25 words
The device of claim 2, wherein said titanium nitride interconnect lines make contact to titanium silicide layers at the surface of said active device regions.
Claim 5
Dependent Claim 34 words
The device of claim 2, wherein ones of said titanium nitride lines also make contact to a gate layer in predetermined locations, said gate layer being polycrystalline and comprising a substantial fraction of silicon.
Claim 6
Dependent Claim 44 words
The device of claim 2, wherein said active device regions are covered by an interlevel dielectric having contact holes filled with metal therein, said metal in said contact holes making direct contact only to portions of said titanium nitride layer at the bottom thereof.
Claim 7
Dependent Claim 37 words
The device of claim 2, wherein said titanium nitride layer extends both over predetermined portions of said device isolation region and also over predetermined portions of titanium silicide layers at the surface of said active device regions.
Claim 8
Dependent Claim 52 words
The device of claim 2, wherein said active devices comprise field effect transistors having gates formed from patterned portions of said first thin film layer, said first thin film layer providing a gate layer, and wherein said lines of said interconnect layer also make contact to said gate layer in predetermined locations.
Claim 9
Dependent Claim 18 words
The device of claim 7, wherein said gate layer is polycrystalline and comprises a substantial fraction of silicon.
Claim 10
Dependent Claim 14 words
The device of claim 8, wherein said gate layer comprises more than 80% silicon.
Claim 11
Dependent Claim 14 words
The device of claim 9, wherein said gate layer consists essentially of polycrystalline silicon.
Claim 12
Dependent Claim 13 words
The device of claim 7, wherein said gate layer comprises a silicide layer.
Claim 13
Dependent Claim 27 words
The device of claim 11, wherein said lines of said interconnect layer also make contact to said silicide layer portion of said gate layer in predetermined locations.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-04-10 1992-10-10 1993-04-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-04-10 1996-10-10 1997-04-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-04-10 2000-10-10 2001-04-11 $7700.00 Window Closed / Lapsed

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