US5655113A — Resynchronization circuit for a memory system and…

Claim 1

Independent Claim 172 words

A resynchronization circuit for processing a stream of data values read from a memory system, said resynchronization circuit comprising: a first in, first out (FIFO) memory device which receives said stream of data values and a first clock signal from said memory system, wherein said data values are sequentially read into said FIFO memory device in response to said first clock signal; a phase locked loop circuit which receives a second clock signal and in response generates an output clock signal which leads in phase said second clock signal, wherein said output clock signal is provided to said FIFO memory device to cause said data values to be sequentially read from said FIFO memory device, thereby generating a stream of data values which is synchronized with said second clock signal; and a latency control circuit coupled to said FIFO memory device which enables said data values to be read from said FIFO memory device only after a selectable delay period which follows the initiation of said read operation from said memory system.

Claim 2

Dependent Claim 172 words

A resynchronization circuit for processing a stream of data values read from a memory system, said resynchronization circuit comprising: a first in, first out (FIFO) memory device which receives said stream of data values and a first clock signal from said memory system, wherein said data values are sequentially read into said FIFO memory device in response to said first clock signal; a phase locked loop circuit which receives a second clock signal and in response generates an output clock signal which leads in phase said second clock signal, wherein said output clock signal is provided to said FIFO memory device to cause said data values to be sequentially read from said FIFO memory device, thereby generating a stream of data values which is synchronized with said second clock signal; and a latency control circuit coupled to said FIFO memory device which enables said data values to be read from said FIFO memory device only after a selectable delay period which follows the initiation of said read operation from said memory system.

Claim 3

Dependent Claim 28 words

The resynchronization circuit of claim 1, wherein said latency control circuit further comprises a programmable register which stores a value indicating the duration of said selectable delay period.

Claim 4

Dependent Claim 127 words

The resynchronization circuit of claim 1, wherein said FIFO memory device further comprises: a plurality of latches connected in parallel between an input lead and an output lead; an input sequencer which receives said first clock signal and in response generates a plurality of input select signals which are provided to said latches, whereby said input select signals cause said data values to be sequentially written into said latches; and an output sequencer which receives said output clock signal and in response generates a plurality of output select signals which are provided to said latches, whereby said output select signals cause said data values to be sequentially read from said latches to generate a output stream of data values which is synchronized with said second clock signal.

Claim 5

Dependent Claim 49 words

The resynchronization circuit of claim 1, further comprising: means for disabling said resynchronization circuit, whereby said stream of data values from said memory system are transmitted directly through said FIFO memory device in an asynchronous manner with respect to the second clock signal when said resynchronization circuit is disabled.

Claim 6

Dependent Claim 53 words

The resynchronization circuit of claim 4, wherein said memory system is located on a semiconductor device having a set of connection pins and said memory system is accessed both synchronously with respect to the second clock signal and asynchronously with respect to the second clock signal using the same set of connection pins.

Claim 7

Independent Claim 157 words

A method of resynchronizing a stream of data values comprising the steps of: detecting a read command signal which initiates a read operation of a stream of data values from a memory system; generating a read enable signal in response to detection of said read command signal; writing said stream of data values to a first in, first out (FIFO) memory device in response to said read enable signal, wherein said writing is performed in response to a first clock signal; generating an output enable signal with a selectable delay in response to said read enable signal; transmitting said output enable signal to said FIFO memory device; and reading said stream of data values out of said FIFO memory device in response to said output enable signal, wherein said reading is performed in response to a second clock signal, thereby synchronizing the stream of data values out of said FIFO memory device with said second clock signal.

Claim 8

Independent Claim 157 words

A method of resynchronizing a stream of data values comprising the steps of: detecting a read command signal which initiates a read operation of a stream of data values from a memory system; generating a read enable signal in response to detection of said read command signal; writing said stream of data values to a first in, first out (FIFO) memory device in response to said read enable signal, wherein said writing is performed in response to a first clock signal; generating an output enable signal with a selectable delay in response to said read enable signal; transmitting said output enable signal to said FIFO memory device; and reading said stream of data values out of said FIFO memory device in response to said output enable signal, wherein said reading is performed in response to a second clock signal, thereby synchronizing the stream of data values out of said FIFO memory device with said second clock signal.

Claim 9

Dependent Claim 71 words

The method of claim 6, further comprising the steps of: providing said second clock signal to a phase locked loop; using said phase locked loop to generate an output clock signal in response to said second clock signal, wherein said output clock signal leads in phase said second clock signal; and controlling the step of reading said stream of data values out of said FIFO memory with said output clock signal.

Claim 10

Dependent Claim 17 words

The method of claim 6, further comprising the step of selecting the duration of said selectable delay.

Claim 11

Dependent Claim 22 words

The method of claim 6, wherein said selectable delay is greater than or equal to the access latency of said memory system.

Claim 12

Dependent Claim 43 words

The method of claim 6, wherein said selectable delay is less than the time which causes data values written to said FIFO memory device to be overwritten by subsequent data values in the absence of a read operation from said FIFO memory device.

Claim 13

Dependent Claim 26 words

The method of claim 6, wherein a data value is read out of said FIFO memory device during each half cycle of said second clock signal.

Claim 14

Dependent Claim 26 words

The method of claim 6, wherein a data value is written into said FIFO memory device during each half clock cycle of said first clock signal.

Claim 15

Dependent Claim 217 words

A resynchonization circuit for reading data values from a dynamic random access memory (DRAM) in response to a system clock signal and a read enable signal, the DRAM having a read access latency, the resynchronization circuit comprising: a delay circuit coupled to receive the system clock signal, wherein the delay circuit generates a first clock signal in response to the system clock signal, the first clock signal having no definite phase relationship with the system clock signal, wherein the delay circuit introduces a delay to the first clock signal which is approximately equal to the read access latency of the DRAM; a first in, first out (FIFO) memory coupled to the delay circuit and the DRAM, wherein the data values read from the DRAM are written to the FIFO memory in response to the first clock signal, and wherein the data values are read from the FIFO memory in response to the system clock signal; and a latency control circuit coupled to the FIFO memory, wherein the latency control circuit generates a control signal to enable the data values to be read from the FIFO memory only after a latency period has expired, the latency period beginning when the read enable signal is asserted and continuing for at least the read access latency of the DRAM array.

Claim 16

Dependent Claim 217 words

A resynchonization circuit for reading data values from a dynamic random access memory (DRAM) in response to a system clock signal and a read enable signal, the DRAM having a read access latency, the resynchronization circuit comprising: a delay circuit coupled to receive the system clock signal, wherein the delay circuit generates a first clock signal in response to the system clock signal, the first clock signal having no definite phase relationship with the system clock signal, wherein the delay circuit introduces a delay to the first clock signal which is approximately equal to the read access latency of the DRAM; a first in, first out (FIFO) memory coupled to the delay circuit and the DRAM, wherein the data values read from the DRAM are written to the FIFO memory in response to the first clock signal, and wherein the data values are read from the FIFO memory in response to the system clock signal; and a latency control circuit coupled to the FIFO memory, wherein the latency control circuit generates a control signal to enable the data values to be read from the FIFO memory only after a latency period has expired, the latency period beginning when the read enable signal is asserted and continuing for at least the read access latency of the DRAM array.

Claim 17

Dependent Claim 20 words

The resynchronization circuit of claim 13 wherein the system clock signal has the same frequency as the first clock signal.

Claim 18

Dependent Claim 95 words

The resynchronization circuit of claim 13, further comprising: a phase locked loop circuit which generates an output clock signal in response to the system clock signal, wherein the output clock signal leads in phase said system clock signal, wherein the FIFO memory is clocked by the output clock signal to read the data values from the FIFO memory; and an output buffer connected to receive the data values read from the FIFO memory, wherein the data values read from the FIFO memory are transmitted through the output buffer in phase with the system clock signal.

Claim 19

Dependent Claim 21 words

The resynchronization circuit of claim 13, wherein the latency control circuit comprises a programmable memory circuit for storing the latency period.

Claim 20

Independent Claim 166 words

A method of reading data values from a dynamic random access memory (DRAM) in response to a system clock signal and a read enable signal, the DRAM having a read access latency, the method comprising the steps of: generating a first clock signal in response to the system clock signal, the first clock signal having no definite phase relationship with the system clock signal, the first clock signal lagging the system clock signal by a delay which is approximately equal to the read access latency of the DRAM; writing data values read from the DRAM into a first in, first out (FIFO) memory in response to the first clock signal; reading data values from the FIFO memory in response to the system clock signal; and enabling the data values to be read the FIFO memory only after a latency period has expired, the latency period beginning when the read enable signal is asserted and continuing for at least the read access latency of the DRAM array.

Claim 21

Independent Claim 166 words

A method of reading data values from a dynamic random access memory (DRAM) in response to a system clock signal and a read enable signal, the DRAM having a read access latency, the method comprising the steps of: generating a first clock signal in response to the system clock signal, the first clock signal having no definite phase relationship with the system clock signal, the first clock signal lagging the system clock signal by a delay which is approximately equal to the read access latency of the DRAM; writing data values read from the DRAM into a first in, first out (FIFO) memory in response to the first clock signal; reading data values from the FIFO memory in response to the system clock signal; and enabling the data values to be read the FIFO memory only after a latency period has expired, the latency period beginning when the read enable signal is asserted and continuing for at least the read access latency of the DRAM array.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-08-04	2001-02-03	2001-08-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-08-04	2005-02-03	2005-08-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-08-04	2009-02-03	2009-08-05	$7700.00	Window Closed / Lapsed

Resynchronization circuit for a memory system and method of operating same

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