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US5214657A
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Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers
Assignee: Micron Technology Inc
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Filing: 1992-06-30
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Granted: 1993-05-25
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Expires: 2012-06-30
Abstract
Abstract The invention relates primarily to wafer-scale integration. Yet in one aspect, circuitry is provided to enable dicing of the wafer to use discrete memory sections thereon as memory chips should the wafer as a whole fail test. In another aspect, error detection and correction circuitry is provided within the street area to detect and correct errors generated within the discrete memory sections where wafer-scale integration manufacturing is successful. In another aspect, clusters of discrete sections of integrated circuitry are provided which include RAM integrated circuitry. One discrete section within the cluster comprises a) control circuitry to control and coordinate operation of discrete sections within the cluster, and b) error detection and correction circuitry to detect and correct errors generated within the discrete sections of RAM integrated circuitry. In still another aspect, test circuitry including fuses are provided within the street area and interconnect with selective portions of different discrete sections of circuitry. Fuses within the test circuitry would be provided and selectively blown to isolate the inoperative areas from each respective memory section, thereby effectively increasing the yield of operable circuitry on the wafer.
Inventors
- 👤 Warren M. Farnworth
- 👤 Kevin Duesman
- 👤 Ed Heitzeberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:48
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G11C29/006; G11C29/83; G11C29/832; H; H10; H10P; H10P74/00; H10P74/23; H10P74/232
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
92 words
A semiconductor wafer comprising: a plurality of discrete memory sections of integrated circuitry, the discrete memory sections being separated by street area; permanent error detection and correction circuitry within the street area to detect and correct errors generated within the discrete memory sections; permanent conductive interconnecting lines extending from the discrete memory sections to the error detection and correction circuitry within the street area; and the semiconductor wafer being maintained as a whole and the error detection and correction circuitry and the interconnecting lines being permanently retained and operable on the wafer.
Claim 2
Dependent Claim
92 words
A semiconductor wafer comprising: a plurality of discrete memory sections of integrated circuitry, the discrete memory sections being separated by street area; permanent error detection and correction circuitry within the street area to detect and correct errors generated within the discrete memory sections; permanent conductive interconnecting lines extending from the discrete memory sections to the error detection and correction circuitry within the street area; and the semiconductor wafer being maintained as a whole and the error detection and correction circuitry and the interconnecting lines being permanently retained and operable on the wafer.
Claim 3
Dependent Claim
28 words
The semiconductor wafer of claim 1 wherein the error correction and detection circuitry is configured to detect and correct errors in a plurality of the discrete memory sections.
Claim 4
Dependent Claim
31 words
The semiconductor wafer of claim 1 wherein the conductive interconnecting line extending to the error detection and correction circuitry includes induced voltage isolating circuitry formed within the respective discrete memory section.
Claim 5
Dependent Claim
43 words
The semiconductor wafer of claim 1 further comprising induced voltage isolating circuitry formed within the discrete memory sections, the induced voltage isolating circuitry connecting with all conductive lines within the discrete memory sections which pass from the discrete sections into the street area.
Claim 6
Dependent Claim
76 words
The semiconductor wafer of claim 1 wherein, the error correction and detection circuitry is configured to detect and correct errors in a plurality of the discrete memory sections; and the discrete memory sections include at least one signal node, the semiconductor wafer further comprising a conductive interface test pad formed in the street area, a conductive interconnecting line extending from the at least one signal node to the conductive interface test pad in the street area.
Claim 7
Dependent Claim
37 words
The semiconductor wafer of claim 5 wherein the conductive interconnecting line extending from the at least one signal node within a respective discrete memory section includes induced voltage isolating circuitry formed within the respective discrete memory section.
Claim 8
Dependent Claim
47 words
The semiconductor wafer of claim 5 wherein the conductive interconnecting lines extending from the at least one signal node within a respective discrete memory section and those extending to the error detection and correction circuitry include induced voltage isolating circuitry formed within the respective discrete memory section.
Claim 9
Dependent Claim
54 words
The semiconductor wafer of claim 1 wherein the discrete memory sections include at least one signal node, the semiconductor wafer further comprising a conductive interface test pad formed in the street area, a conductive interconnecting line extending from the at least one signal node to the conductive interface test pad in the street area.
Claim 10
Dependent Claim
37 words
The semiconductor wafer of claim 8 wherein the conductive interconnecting line extending from the at least one signal node within a respective discrete memory section includes induced voltage isolating circuitry formed within the respective discrete memory section.
Claim 11
Dependent Claim
44 words
The semiconductor wafer of claim 9 wherein the induced voltage isolating circuitry comprises a transistor within the respective discrete memory section, the transistor having a control line which is biased within the respective discrete memory section to place the transistor in an off condition.
Claim 12
Dependent Claim
37 words
The semiconductor wafer of claim 1 further comprising integrated test circuitry formed within the street area, the test circuitry being in electrical communication with selected discrete memory sections to facilitate testing of the selected discrete memory sections.
Claim 13
Dependent Claim
24 words
The semiconductor wafer of claim 11 wherein the integrated test circuitry comprises circuitry enabling testing of several selected discrete memory sections simultaneously in parallel.
Claim 14
Dependent Claim
60 words
The semiconductor wafer of claim 1 wherein the error correction and detection circuitry is configured to detect and correct errors in a plurality of the discrete memory sections; and further comprising integrated test circuitry formed within the street area, the test circuitry being in electrical communication with selected discrete memory sections to facilitate testing of the selected discrete memory sections.
Claim 15
Dependent Claim
24 words
The semiconductor wafer of claim 13 wherein the integrated test circuitry comprises circuitry enabling testing of several selected discrete memory sections simultaneously in parallel.
Claim 16
Dependent Claim
71 words
The semiconductor wafer of claim 1 wherein the discrete memory section include at least one signal node, the semiconductor wafer further comprising: integrated test circuitry formed within the street area to facilitate testing of selected discrete memory sections; a conductive interconnecting line extending from the at least one signal node to the integrated test circuitry; and the integrated test circuitry including a conductive interface test pad formed in the street area.
Claim 17
Dependent Claim
37 words
The semiconductor wafer of claim 15 wherein the conductive interconnecting line extending from the at least one signal node within a respective discrete memory section includes induced voltage isolating circuitry formed within the respective discrete memory section.
Claim 18
Dependent Claim
44 words
The semiconductor wafer of claim 16 wherein the induced voltage isolating circuitry comprises a transistor within the respective discrete memory section, the transistor having a control line which is biased within the respective discrete memory section to place the transistor in an off condition.
Claim 19
Dependent Claim
16 words
The semiconductor wafer of claim 1 further comprising refresh controller/memory management circuitry formed on the wafer.
Claim 20
Dependent Claim
30 words
The semiconductor wafer of claim 1 further comprising amplifier/driver circuitry formed on the wafer to improve speed of devices on the wafer that the amplifier driver circuitry is associated with.
Claim 21
Dependent Claim
158 words
A semiconductor wafer comprising: a cluster of discrete sections of integrated circuitry, the discrete sections being separated within the cluster by street area, the discrete sections each being at least one signal node; a plurality of the discrete sections within the cluster comprising RAM integrated circuitry; one of the discrete sections within the cluster comprising a) control circuitry to control and coordinate operation of discrete sections within the cluster, and b) error detection and correction circuitry to detect and correct errors generated within the discrete sections of RAM integrated circuitry; a plurality of conductive interface test pads formed within street area on the wafer; permanent conductive interconnecting lines extending from selective signal nodes of selective discrete sections within the cluster, the conductive interconnecting lines extending to selective conductive interface test pads within street area on the wafer; and the semiconductor wafer being maintained as a whole and the interconnecting lines being permanently retained and operable on the wafer.
Claim 22
Dependent Claim
158 words
A semiconductor wafer comprising: a cluster of discrete sections of integrated circuitry, the discrete sections being separated within the cluster by street area, the discrete sections each being at least one signal node; a plurality of the discrete sections within the cluster comprising RAM integrated circuitry; one of the discrete sections within the cluster comprising a) control circuitry to control and coordinate operation of discrete sections within the cluster, and b) error detection and correction circuitry to detect and correct errors generated within the discrete sections of RAM integrated circuitry; a plurality of conductive interface test pads formed within street area on the wafer; permanent conductive interconnecting lines extending from selective signal nodes of selective discrete sections within the cluster, the conductive interconnecting lines extending to selective conductive interface test pads within street area on the wafer; and the semiconductor wafer being maintained as a whole and the interconnecting lines being permanently retained and operable on the wafer.
Claim 23
Dependent Claim
35 words
The semiconductor wafer of claim 20 further comprising integrated test circuitry formed within street area on the wafer to facilitate testing of the selective discrete sections, the test circuitry connecting with the conductive interconnecting lines.
Claim 24
Dependent Claim
24 words
The semiconductor wafer of claim 21 wherein the integrated test circuitry comprises circuitry enabling testing of several selected discrete memory sections simultaneously in parallel.
Claim 25
Dependent Claim
27 words
The semiconductor wafer of claim 20 wherein the conductive interconnecting lines extending from the selective signal nodes include induced voltage isolating circuitry formed within respective discrete sections.
Claim 26
Dependent Claim
42 words
The semiconductor wafer of claim 23 wherein the induced voltage isolating circuitry comprises a transistor within the respective discrete section, the transistor having a control line which is biased within the respective discrete section to place the transistor in an off condition.
Claim 27
Dependent Claim
68 words
The semiconductor wafer of claim 20 wherein the conductive interconnecting lines extending from the selective signal nodes of the selective discrete sections within the cluster include induced voltage isolating circuitry formed within respective discrete sections; and the semiconductor wafer further comprising integrated test circuitry formed within street area on the wafer to facilitate testing of the selective discrete sections, the test circuitry connecting with the conductive interconnecting lines.
Claim 28
Dependent Claim
42 words
The semiconductor wafer of claim 25 wherein the induced voltage isolating circuitry comprises a transistor within the respective discrete section, the transistor having a control line which is biased within the respective discrete section to place the transistor in an off condition.
Claim 29
Dependent Claim
24 words
The semiconductor wafer of claim 25 wherein the integrated test circuitry comprises circuitry enabling testing of several selected discrete memory sections simultaneously in parallel.
Claim 30
Dependent Claim
45 words
The semiconductor wafer of claim 20 further comprising induced voltage isolating circuitry formed within the discrete sections containing RAM integrated circuitry, the induced voltage isolating circuitry connecting with all conductive lines within the discrete sections which pass from the discrete sections into the street area.
Claim 31
Dependent Claim
37 words
The semiconductor wafer of claim 28 wherein the induced voltage isolating circuitry comprises a transistor, the transistor having a control line which is biased within the respective discrete section to place the transistor in an off condition.
Claim 32
Dependent Claim
16 words
The semiconductor wafer of claim 20 further comprising refresh controller/memory management circuitry formed on the wafer.
Claim 33
Dependent Claim
30 words
The semiconductor wafer of claim 20 further comprising amplifier/driver circuitry formed on the wafer to improve speed of devices on the wafer that the amplifier driver circuitry is associated with.
Claim 34
Dependent Claim
143 words
A semiconductor wafer comprising: a plurality of discrete memory sections of integrated circuitry, the discrete memory sections being separated by street area, the discrete memory sections including at least one signal node; permanent test circuitry within the street area, the test circuitry comprising fuses within the street area, the test circuitry and fuses interconnecting with selective regions within the plurality of the discrete memory sections to enable selective electrical isolation of such regions and to enable selective combination of such regions from different discrete memory sections, the test circuitry including a plurality of conductive interface test pads formed within the street area; permanent conductive interconnecting lines extending from signal nodes of discrete memory sections to the test circuitry; and the semiconductor wafer being maintained as a whole and the test circuitry and conductive interconnecting lines being permanently retained and operable on the wafer.
Claim 35
Dependent Claim
143 words
A semiconductor wafer comprising: a plurality of discrete memory sections of integrated circuitry, the discrete memory sections being separated by street area, the discrete memory sections including at least one signal node; permanent test circuitry within the street area, the test circuitry comprising fuses within the street area, the test circuitry and fuses interconnecting with selective regions within the plurality of the discrete memory sections to enable selective electrical isolation of such regions and to enable selective combination of such regions from different discrete memory sections, the test circuitry including a plurality of conductive interface test pads formed within the street area; permanent conductive interconnecting lines extending from signal nodes of discrete memory sections to the test circuitry; and the semiconductor wafer being maintained as a whole and the test circuitry and conductive interconnecting lines being permanently retained and operable on the wafer.
Claim 36
Dependent Claim
23 words
The semiconductor wafer of claim 32 wherein the test circuitry comprises circuitry enabling testing of several selected discrete memory sections simultaneously in parallel.
Claim 37
Dependent Claim
27 words
The semiconductor wafer of claim 32 wherein the conductive interconnecting lines extending from the signal nodes include induced voltage isolating circuitry formed within respective discrete memory sections.
Claim 38
Dependent Claim
56 words
The semiconductor wafer of claim 34 wherein the induced voltage isolating circuitry comprises a transistor within the respective discrete memory section, the transistor having a control line which is biased within the respective discrete memory section to place the transistor in an off condition, the control line connecting with the test circuitry within the street area.
Claim 39
Dependent Claim
44 words
The semiconductor wafer of claim 32 wherein: the test circuitry comprises circuitry enabling testing of several selected discrete memory sections simultaneously in parallel; and the conductive interconnecting lines extending from the signal nodes include induced voltage isolating circuitry formed within respective discrete memory sections.
Claim 40
Dependent Claim
56 words
The semiconductor wafer of claim 36 wherein the induced voltage isolating circuitry comprises a transistor within the respective discrete memory section, the transistor having a control line which is biased within the respective discrete memory section to place the transistor in an off condition, the control line connecting with the test circuitry within the street area.
Claim 41
Dependent Claim
43 words
The semiconductor wafer of claim 32 further comprising induced voltage isolating circuitry formed within the discrete memory sections, the induced voltage isolating circuitry connecting with all conductive lines within the discrete memory sections which pass from the discrete sections into the street area.
Claim 42
Dependent Claim
16 words
The semiconductor wafer of claim 32 further comprising refresh controller/memory management circuitry formed on the wafer.
Claim 43
Dependent Claim
30 words
The semiconductor wafer of claim 32 further comprising amplifier/driver circuitry formed on the wafer to improve speed of devices on the wafer that the amplifier driver circuitry is associated with.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |