US4866508A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit packaging configuration for rapid customized design and unique test capability
Assignee: Lockheed Martin Corp
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Filing: 1986-09-26
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Granted: 1989-09-12
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Expires: 2006-09-26
Abstract
Abstract The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.
Inventors
- 👤 Charles W. Eichelberger
- 👤 II Kenneth B. Welles
- 👤 Robert J. Wojnarowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505; H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
53 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate so as to define a channel between said chips, said chips having interconnect pads thereon; and a metallization pattern disposed on said substrate, said pattern including a plurality of periodically interrupted conductors extending along said channel.
Claim 2
Dependent Claim
53 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate so as to define a channel between said chips, said chips having interconnect pads thereon; and a metallization pattern disposed on said substrate, said pattern including a plurality of periodically interrupted conductors extending along said channel.
Claim 3
Dependent Claim
34 words
The package of claim 1 further including an insulative overlay layer disposed over said chips and said substrate, said overlay layer including apertures therein in alignment with at least some of said interconnect pads.
Claim 4
Dependent Claim
73 words
The package of claim 2 further including a second insulative overlay layer having apertures therein aligned with at least some of said interconnect pads and also including a second metallization pattern connecting, through said apertures, select interconnect pads, said second metallization pattern also including at least some apertures therein positioned over said interrupted metallization patterns and including metallization patterns thereon for connecting to and for electrically bridging select ones of said interrupted conductors.
Claim 5
Dependent Claim
29 words
The package of claim 1 in which said integrated circuit chips are disposed in pairs, each chip of a pair being disposed on an opposite side of said channel.
Claim 6
Dependent Claim
19 words
The package of claim 4 in which said interruptions in said metallization pattern are positioned between said chip pairs.
Claim 7
Dependent Claim
24 words
The package of claim 1 in which said substrate comprises material selected from the group consisting of ceramics, metal, plastics, composites, silicon and glass.
Claim 8
Dependent Claim
14 words
The package of claim 1 in which said overlay layer comprises a polymer film.
Claim 9
Dependent Claim
18 words
The package of claim 1 in which a separate layer is employed to supply power to said chips.
Claim 10
Dependent Claim
16 words
The package of claim 1 in which said substrate includes wells for placement of said chips.
Claim 11
Dependent Claim
82 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate so as to define a channel between said chips, said chips having interconnect pads thereon; and an insulative overlay layer disposed over said chips and said substrate, said overlay layer having a metallization pattern thereon, said pattern including a plurality of periodically interrupted conductors extending along said channel, said overlay layer also including apertures therein in alignment with at least some of said interconnect pads.
Claim 12
Dependent Claim
82 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate so as to define a channel between said chips, said chips having interconnect pads thereon; and an insulative overlay layer disposed over said chips and said substrate, said overlay layer having a metallization pattern thereon, said pattern including a plurality of periodically interrupted conductors extending along said channel, said overlay layer also including apertures therein in alignment with at least some of said interconnect pads.
Claim 13
Dependent Claim
76 words
The package of claim 10 which further includes a second overlay layer having apertures therein aligned with at least some of said interconnect pads and also including a second metallization pattern connecting, through apertures in said second layer, select interconnect pads, said second metallization pattern also including at least some apertures therein positioned over said interrupted metallization pattern and including metallization patterns thereon for connecting to and for electrically bridging select ones of said interrupted conductors.
Claim 14
Dependent Claim
72 words
A multifunction circuit comprising: a plurality of functional circuit blocks having input and output lines; decoding means for selecting one of said functional blocks; means for storing test data to be supplied to said input lines, said input line being selectable in response to said decoding means; means for storing data from said output lines of said circuit blocks; and means for receiving test data from said means for storing test data.
Claim 15
Dependent Claim
72 words
A multifunction circuit comprising: a plurality of functional circuit blocks having input and output lines; decoding means for selecting one of said functional blocks; means for storing test data to be supplied to said input lines, said input line being selectable in response to said decoding means; means for storing data from said output lines of said circuit blocks; and means for receiving test data from said means for storing test data.
Claim 16
Dependent Claim
23 words
The multifunction circuit of claim 12 in which at least one of said storing means and said receiving means comprises a shift register.
Claim 17
Dependent Claim
86 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate, said chips having interconnect pads thereon; and at least one polymer layer disposed over said chips and said substrate, said polymer layer including apertures therein in alignment with at least some of said interconnect pads; wherein at least one of said chips includes a plurality of functional circuit blocks having input and output means and decoding means for selecting one function from within at least one of said blocks.
Claim 18
Dependent Claim
86 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate, said chips having interconnect pads thereon; and at least one polymer layer disposed over said chips and said substrate, said polymer layer including apertures therein in alignment with at least some of said interconnect pads; wherein at least one of said chips includes a plurality of functional circuit blocks having input and output means and decoding means for selecting one function from within at least one of said blocks.
Claim 19
Dependent Claim
45 words
The circuit of claim 14 in which at least said function blocks include: means for storing test data to be supplied to said input means; means for storing data from said output means; and means for receiving test data from said test data storing means.
Claim 20
Dependent Claim
25 words
The circuit of claim 14 further including a metallization pattern disposed on said polymer layer so as to interconnect select interconnect pads on said chips.
Claim 21
Dependent Claim
115 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate so as to define a channel between said chips, said chips having interconnect pads thereon; at least one polymer layer disposed over said chips and said substrate, said polymer layer including apertures therein in alignment with at least some of said interconnect pads; wherein at least one of said chips includes a plurality of functional circuit blocks having input and output means and decoding means for selecting one function from within at least one of said blocks; and a metallization pattern disposed on said substrate, said pattern including a plurality of periodically interrupted conductors extending along said channel.
Claim 22
Dependent Claim
115 words
An integrated circuit package comprising: a substrate; a plurality of integrated circuit chips disposed on said substrate so as to define a channel between said chips, said chips having interconnect pads thereon; at least one polymer layer disposed over said chips and said substrate, said polymer layer including apertures therein in alignment with at least some of said interconnect pads; wherein at least one of said chips includes a plurality of functional circuit blocks having input and output means and decoding means for selecting one function from within at least one of said blocks; and a metallization pattern disposed on said substrate, said pattern including a plurality of periodically interrupted conductors extending along said channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |