Method of manufacturing electronic device having multilayer wiring structure

Claim 2

In a method of manufacturing on a substrate an electronic device including a multilayer wiring structure comprising forming an interlayer insulation layer comprised of a thermosetting polyimide between a previously formed respective lower metal layer of wiring and a subsequently formed respective upper metal layer of wiring, said method comprising forming said multilayer wiring structure to have at least one of said interlayer insulation layers between at least one pair of said respective upper and lower metal wiring layers, the improvement comprising using as the thermoset polyimide an addition polymerization type polyimide comprising imide rings in the recurring groups and reactive end groups with triple bonds.

Claim 3

The method of claim 1, wherein each said recurring group comprising a tetravalent aromatic group between two of said imide rings.

Claim 4

The method of claim 2, wherein said addition polymerization type polyimide being represented by the formula: ##STR8##

Claim 5

The method of claim 1, wherein each said reactive end group with a triple bond comprising a group that is the ethynyl or carbonitril group.

Claim 6

The method of claim 2, wherein said addition polymerization type polyimide is represented by the formula: ##STR9## wherein R is a divalent aromatic or aliphatic radical having no active hydrogen, and m is a positive integer, each Y group comprising one of said end groups with a triple bond.

Claim 7

The method of claim 4, wherein each of said reactive end groups with a triple bond comprises ##STR10##

Claim 8

The method of claim 1, 2, 3, 5, or 6 wherein each said addition polymerization type polyimide has a molecular weight range of from approximately 800 to approximately 20,000.

Claim 9

The method of claim 1, 2, 3, 5 or 6 wherein said addition polymerization type polyimide of at least one of said at least one interlayer insulating layer(s) is soluble in acetone.

Claim 10

The method of claim 1, 2, 3, 5 or 6, wherein the formation of each polyimide interlayer insulation layer is carried out by coating the substrate having formed thereon said respective lower metal layer of wiring with a coating solution of the polyimide in a solvent selected from the group consisting of N-methyl-2-pyrrolidone, dimethylacetamide and ketones, the polyimide concentration in the coating solution being not more than 55% by weight.

Claim 11

The method of claim 1, 2, 3, 5 or 6, the electronic device comprising built up circuit elements that are selectively covered with a protective layer to define exposed and nonexposed portions of said circuit elements of said device, the forming of said multilayer wiring structure comprising the steps of: (A) forming a first metal layer of said multilayer wiring structure to have a predetermined pattern on said semiconductor substrate having said build-up circuit elements with said exposed and non-exposed portions; (B) subsequently performing at least one sequence of the following steps (i) to (iii): (i) applying the addition polymerization type polyimide to form a polyimide layer over said substrate with said circuit elements and on the uppermost wiring layer previously formed thereon as the respective lower wiring layer, followed by pre-curing of the polyimide layer; (ii) imparting a predetermined pattern to the pre-cured polyimide layer, to selectively form openings in at least the uppermost polyimide layer to selectively expose the underlying wiring including said respective lower wiring layer; and (iii) selectively forming the respective upper metal layer of wiring on predetermined portions of the polyimide layer and said openings therein, said forming of said multilayer wiring structure subsequently comprising: (C) applying the addition polymerization type polyimide to form a final polyimide layer, followed by precuring the final polyimide layer; (D) selectively providing openings for electrical contact to the metal wirings under the final polyimide insulation layer, and (E) simultaneously completing the curing of all of said polyimide layers.

Claim 12

The method of claim 1, 2, 3, 5 or 6, the electronic device comprising a bubble memory device, said substrate comprising a bubble memory crystalline substrate, said method comprising the steps of: forming a metal conductor pattern on said substrate as the first respective lower metal layer of wiring forming the first interlayer insulation layer with a predetermined pattern; and forming a permalloy layer of a predetermined pattern on said polyimide layer as the first respective upper metal layer of wiring.

Claim 13

The method of claim 1, 2, 3, 5 or 6, wherein the electronic device having the multilayer wiring structure is a thin film magnetic head and said method comprises the steps of: (i) forming on the substrate a lower metal wiring layer of a magnetic layer having a predetermined pattern; (ii) applying the addition polymerization type polyimide to form a polyimide layer, followed by curing the polyimide layer and, further, by patterning the cured polyimide layer to form an interlayer insulation layer; (iii) forming an upper metal wiring layer in a coil form on said interlayer insulation layer; (iv) forming a second insulation layer in the manner of step (ii) above on said substrate with said lower magnetic layer, said first insulation layer and said metal conductor layer; and then (v) forming an upper magnetic layer with a predetermined pattern on said second insulating layer.

Claim 14

The method of claim 12, wherein a layer comprised of Al 2 O 3 , TiO 2 and Cr 2 O 3 is formed between the steps of (i) and (ii).

Claim 15

The method of claim 12, wherein a layer comprised of at least one metal oxide selected from the group consisting of Al 2 O 3 , TiO 2 and Cr 2 O 3 is formed between the steps of (iv) and (v).

Claim 16

The method of claim 12, wherein two layers, each comprised of at least one metal oxide selected from the group consisting of Al 2 O 3 , TiO 2 and Cr 2 O 3 are formed, one being between the steps of (i) and (ii), and the other between the steps of (iv) and (v).

Claim 17

The method of claim 5, wherein R is ##STR11##

Claim 18

The method of claim 7, said molecular weight range being from approximately 1,000 to approximately 10,000.

Claim 19

The method of claim 1, 2, 3, 5 or 6, said device comprising at least two of said interlayer insulation layers, said method comprising first precuring individually each said interlayer insulation layer and subsequently simultaneously completing the curing of all of said interlayer insulation layers.

Claim 20

The method of claim 1, 2, 3, 5 or 6, comprising forming at least one interlayer insulating layer directly on the surface of said substrate with said first metal layer of wiring.

Claim 21

The method of claim 1, 2, 3, 5 or 6, said device comprising at least two of said interlayer insulation layers, the surface of the first interlayer insulation layer in contact with the second insulation layer being the original surface of the first interlayer insulation layer as formed.

Claim 22

The method of claim 10 comprising precuring each said layer of addition polyimide at a temperature of up to approximately 250° C., and simultaneously completing the curing of all said layers of the addition polyimide at a temperature of up to approximately 350° C.

Claim 23

The method of claim 18, comprising precuring each said interlayer insulating layer at a temperature of up to approximately 250° C.; and simultaneously completing the curing of all said layers at a temperature of up to approximately 350° C.

Claim 24

The method of claim 11, comprising selectively forming an insulation layer on said metal conductor pattern prior to forming said first interlayer insulation layer.

Claim 25

The method of claim 11, comprising completely curing said first interlayer insulation layer prior to forming said permalloy layer.

Claim 26

The method of claim 9, said solvent comprising dimethyl acetamide, said method comprising forming at least one of said interlayer insulating layers with a surface roughness R-max value of less than 0.001 microns.

Claim 27

The method of claim 1, 2 or 3 comprising forming a layer of amino silane on said substrate and the first metal layer of wiring prior to forming the first interlayer insulating layer.

Claim 28

The method of claim 1, 2 or 3 comprising forming a respective lower layer of metal wiring of aluminum of up to 0.9 microns thickness, and forming the first interlayer insulating layer to have an undulation over the edge of said first wiring layer of less than approximately 0.1 microns.

Claim 29

The method of claim 2 or 5, each said reactive end group with a triple bond comprising a group that is the ethynyl or carbonyl group.