US3781683A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
Assignee: International Business Machines Corp
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Filing: 1971-03-30
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Granted: 1973-12-25
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Expires: 1991-03-30
Abstract
Abstract A test circuit configuration for a monolithic integrated semiconductor circuit structure containing a plurality of substantially aligned test contact with which a corresponding plurality of contactors in a testing apparatus head are engaged to provide the input/output points required for the test. The contacts are connected to testing circuits containing active and passive devices in the monolithic semiconductor structure in such a manner that no two adjacent contacts are in the same testing circuit. In a particular configuration, each testing circuit contains only alternate aligned contacts. In wafer testing, the circuit configurations are disposed in the horizontal and vertical kerfs which in effect surround each chip, and a first test circuit configuration is repeated in the horizontal kerf while a second test circuit configuration is repeated in the vertical kerf.
Inventors
- 👤 L Freed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318538
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
274 words
In a testing system of monolithic integrated semiconductor circuit structures, the combination of a wafer containing an array of integrated circuit chips spaced from each other by horizontal and vertical kerfs, first and second test circuit configurations in said kerfs, each configuration comprising a plurality of substantially aligned contacts, and a plurality of testing circuits, each comprising at least one active or passive device and conductive means connecting said at least one device with at least two of said contacts exclusively, said test circuIt configurations being arranged so that each testing circuit contains only alternate contacts, said first test circuit configuration being repeated in a sequential plurality of vertical kerfs and said second test circuit configuration being repeated in a sequential plurality of horizontal kerfs, and a tester contact member comprising a plurality of contactors arranged in a pair of vertical rows and a pair of horizontal rows for respectively contacting the aligned contacts in the pair of vertical kerfs and the pair of horizontal kerfs surrounding a chip, said first vertical row of contactors being arranged to contact alternate contacts in the first vertical kerf and said second vertical row of contactors being arranged to contact the opposite alternate contacts in the second vertical kerf, and said first horizontal row of contactors being arranged to contact alternate contacts in the first horizontal kerf and said second horizontal row of contactors being arranged to contact the opposite alternative contacts in the second horizontal kerf, and means for stepping the tester contact member across the wafer in the horizontal and in the vertical directions whereby the tester contacts the kerfs surrounding a plurality of chips.
Claim 2
Dependent Claim
274 words
In a testing system of monolithic integrated semiconductor circuit structures, the combination of a wafer containing an array of integrated circuit chips spaced from each other by horizontal and vertical kerfs, first and second test circuit configurations in said kerfs, each configuration comprising a plurality of substantially aligned contacts, and a plurality of testing circuits, each comprising at least one active or passive device and conductive means connecting said at least one device with at least two of said contacts exclusively, said test circuIt configurations being arranged so that each testing circuit contains only alternate contacts, said first test circuit configuration being repeated in a sequential plurality of vertical kerfs and said second test circuit configuration being repeated in a sequential plurality of horizontal kerfs, and a tester contact member comprising a plurality of contactors arranged in a pair of vertical rows and a pair of horizontal rows for respectively contacting the aligned contacts in the pair of vertical kerfs and the pair of horizontal kerfs surrounding a chip, said first vertical row of contactors being arranged to contact alternate contacts in the first vertical kerf and said second vertical row of contactors being arranged to contact the opposite alternate contacts in the second vertical kerf, and said first horizontal row of contactors being arranged to contact alternate contacts in the first horizontal kerf and said second horizontal row of contactors being arranged to contact the opposite alternative contacts in the second horizontal kerf, and means for stepping the tester contact member across the wafer in the horizontal and in the vertical directions whereby the tester contacts the kerfs surrounding a plurality of chips.
Claim 3
Dependent Claim
39 words
The testing system of claim 1 wherein the stepping means step the tester contact member in steps of one chip each in both directions whereby all of the kerf contacts surrounding each chip tested are contacted by said member.
Claim 4
Dependent Claim
176 words
In a testing system for monolithic integrated semiconductor circuit structures, the combination of a test circuit configuration in said monolithic integrated circuit comprising a plurality of substantially aligned spaced contacts, and a plurality of testing circuits, each comprising at least one active or passive device and conductive means connecting said at least one device with at least two of said contacts exclusively and each of said testing circuits being arranged so that at least one of its contacts is adapted to receive an input test signal and at least one contact produces an output test signal, said test circuit configuration being arranged so that each testing circuit contains only alternate contacts, and a tester contact member comprising a plurality of contactors adapted to engage sets of alternate aligned contacts, said contactors each having a dimension in the plane of said engagement at least equal to the space between adjacent aligned contacts, and means for applying test input signals through said contactors to said contacts and for sensing test output signals from said contacts through said contactors.
Claim 5
Dependent Claim
176 words
In a testing system for monolithic integrated semiconductor circuit structures, the combination of a test circuit configuration in said monolithic integrated circuit comprising a plurality of substantially aligned spaced contacts, and a plurality of testing circuits, each comprising at least one active or passive device and conductive means connecting said at least one device with at least two of said contacts exclusively and each of said testing circuits being arranged so that at least one of its contacts is adapted to receive an input test signal and at least one contact produces an output test signal, said test circuit configuration being arranged so that each testing circuit contains only alternate contacts, and a tester contact member comprising a plurality of contactors adapted to engage sets of alternate aligned contacts, said contactors each having a dimension in the plane of said engagement at least equal to the space between adjacent aligned contacts, and means for applying test input signals through said contactors to said contacts and for sensing test output signals from said contacts through said contactors.
Claim 6
Independent Claim
147 words
A method of testing monolithic integrated semiconductor circuit structures which permits minimal spacing between test contacts on said structures comprising arranging in said monolithic integrated circuit a test circuit configuration containing a plurality of substantially aligned test contacts and a plurality of testing circuits, each comprising at least one active or passive device connected to at least two of said test contacts exclusively so that each testing circuit contains only alternate test contacts and each of said testing circuits being arranged so that at least one of its contacts is adapted to receive an input test signal and at least one contact produces an output test signal, and contacting with testing means a first set of alternate test contacts followed by contacting with said testing means a second set of opposite alternative test contacts whereby all of the aligned test contacts in said testing circuits are contacted.
Claim 7
Independent Claim
147 words
A method of testing monolithic integrated semiconductor circuit structures which permits minimal spacing between test contacts on said structures comprising arranging in said monolithic integrated circuit a test circuit configuration containing a plurality of substantially aligned test contacts and a plurality of testing circuits, each comprising at least one active or passive device connected to at least two of said test contacts exclusively so that each testing circuit contains only alternate test contacts and each of said testing circuits being arranged so that at least one of its contacts is adapted to receive an input test signal and at least one contact produces an output test signal, and contacting with testing means a first set of alternate test contacts followed by contacting with said testing means a second set of opposite alternative test contacts whereby all of the aligned test contacts in said testing circuits are contacted.
Claim 8
Dependent Claim
62 words
The method of claim 4 wherein a plurality of said test circuit configurations are arranged in an integrated circuit wafer, containing an array of integrated circuit chips spaced from each other by parallel kerf, so that each of said plurality of test circuit configurations is in a sequential parallel kerf, and said contacting step is sequentially repeated for each test circuit conFiguration.
Claim 9
Dependent Claim
154 words
In a testing system for monolithic integrated semi-conductor circuit structures, the combination of a test circuit configuration in said monolithic integrated circuit comprising a plurality of substantially aligned spaced contacts, and a plurality of testing circuits, each comprising at least one active or passive device and conductive means connecting said at least one device with at least two of said contacts exclusively and each of said testing circuits being arranged so that at least one of its contacts is adapted to receive an input test signal and at least one contact produces an output test signal, said test circuit configuration being arranged so that each testing circuit contains only alternate contacts, and a tester contact member comprising a plurality of contactors adapted to engage sets of alternate aligned contacts, and means for applying test input signals through said contactors to said contacts and for sensing test output signals from said contacts through said contactors.
Claim 10
Dependent Claim
154 words
In a testing system for monolithic integrated semi-conductor circuit structures, the combination of a test circuit configuration in said monolithic integrated circuit comprising a plurality of substantially aligned spaced contacts, and a plurality of testing circuits, each comprising at least one active or passive device and conductive means connecting said at least one device with at least two of said contacts exclusively and each of said testing circuits being arranged so that at least one of its contacts is adapted to receive an input test signal and at least one contact produces an output test signal, said test circuit configuration being arranged so that each testing circuit contains only alternate contacts, and a tester contact member comprising a plurality of contactors adapted to engage sets of alternate aligned contacts, and means for applying test input signals through said contactors to said contacts and for sensing test output signals from said contacts through said contactors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |