US5091883A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory and microprocessor
Assignee: Hitachi Ltd
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Filing: 1990-07-13
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Granted: 1992-02-25
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Expires: 2010-07-13
Abstract
Abstract An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.
Inventors
- 👤 Nozomu Matsuzaki
- 👤 Takashi Akioka
- 👤 Masahiro Iwamura
- 👤 Atushi Hiraishi
- 👤 Tatsumi Yamauchi
- 👤 Yuji Yokoyama
- 👤 Yutaka Kobayashi
- 👤 Hideaki Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C5/00; G11C5/06; G11C5/063
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
195 words
A semiconductor memory including: a rectangular semiconductor chip; a plurality of memory cell blocks formed with a plurality of memory cells disposed in alignment within a plurality of rectangular areas on the upper surface of said semiconductor chip, which are arrayed to be disposed in alignment spaced apart from one another with passways being interposed between the adjacent areas; a plurality of input pads formed in the peripheral region on the upper surface of said semiconductor chip; and at least one input buffer provided on the upper surface of said semiconductor chip, and processing an external signal which is input from one of said input pads, and the processed signal being transmitted to the memory cell in the memory cell block group including at least two said memory cell blocks directly or via a logic circuit: wherein said input buffer is provided in one of said passways, which is the closest to a line for equally dividing said memory cell block group longitudinally or laterally into two sections, said passway interposing between the adjacent memory cell blocks belonging to said memory cell block group to which the processed signal of said input buffer is transmitted.
Claim 2
Dependent Claim
195 words
A semiconductor memory including: a rectangular semiconductor chip; a plurality of memory cell blocks formed with a plurality of memory cells disposed in alignment within a plurality of rectangular areas on the upper surface of said semiconductor chip, which are arrayed to be disposed in alignment spaced apart from one another with passways being interposed between the adjacent areas; a plurality of input pads formed in the peripheral region on the upper surface of said semiconductor chip; and at least one input buffer provided on the upper surface of said semiconductor chip, and processing an external signal which is input from one of said input pads, and the processed signal being transmitted to the memory cell in the memory cell block group including at least two said memory cell blocks directly or via a logic circuit: wherein said input buffer is provided in one of said passways, which is the closest to a line for equally dividing said memory cell block group longitudinally or laterally into two sections, said passway interposing between the adjacent memory cell blocks belonging to said memory cell block group to which the processed signal of said input buffer is transmitted.
Claim 3
Dependent Claim
33 words
The semiconductor memory according to claim 1, wherein the external signal input into said input buffer is one of signals such as address signals, write enable signals, write data and address strobe signals.
Claim 4
Dependent Claim
46 words
The semiconductor memory according to claim 1, wherein the external signal input into said input buffer is an address signal, said logic circuit is an address decoder whose logic element at least a primary stage is disposed in said passway where said input buffer is provided.
Claim 5
Dependent Claim
34 words
The semiconductor memory according to claim 1, wherein said input pads are located in a portion adjacent to said passway where said input buffer is provided, within the peripheral region of said semiconductor chip.
Claim 6
Dependent Claim
34 words
The semiconductor memory according to claim 2, wherein said input pads are located in a portion adjacent to said passway where said input buffer is provided, within the peripheral region of said semiconductor chip.
Claim 7
Dependent Claim
34 words
The semiconductor memory according to claim 3, wherein said input pads are located in a portion adjacent to said passway where said input buffer is provided, within the peripheral region of said semiconductor chip.
Claim 8
Dependent Claim
188 words
A microprocessor comprising: a central processing unit and a memory which are formed on the upper surface of a semiconductor chip; said memory including a plurality of memory cell blocks formed with a plurality of memory cells disposed in alignment within a plurality of rectangular areas on the upper surface of said semiconductor chip, which are arrayed to be disposed in alignment apart from one another with passways being interposed between the adjacent areas, and at least one input buffer, said input buffer being adapted to process an external signal which is input from said central processing unit so as to transmit the processed signal to the memory cells of a memory cell block group including at least two said memory cell blocks directly or via a logic circuit: wherein said input buffer is provided in one of said passways, which is the closest to a line for equally dividing said memory cell block group longitudinally or laterally into two sections, said passway interposing between the adjacent memory cell blocks belonging to said memory cell block group to which the processed signal of said input buffer is transmitted.
Claim 9
Dependent Claim
188 words
A microprocessor comprising: a central processing unit and a memory which are formed on the upper surface of a semiconductor chip; said memory including a plurality of memory cell blocks formed with a plurality of memory cells disposed in alignment within a plurality of rectangular areas on the upper surface of said semiconductor chip, which are arrayed to be disposed in alignment apart from one another with passways being interposed between the adjacent areas, and at least one input buffer, said input buffer being adapted to process an external signal which is input from said central processing unit so as to transmit the processed signal to the memory cells of a memory cell block group including at least two said memory cell blocks directly or via a logic circuit: wherein said input buffer is provided in one of said passways, which is the closest to a line for equally dividing said memory cell block group longitudinally or laterally into two sections, said passway interposing between the adjacent memory cell blocks belonging to said memory cell block group to which the processed signal of said input buffer is transmitted.
Claim 10
Dependent Claim
32 words
The microprocessor according to claim 7, wherein the external signal input into said input buffer is one of signals such as address signals, write enable signals, write data and address strobe signals.
Claim 11
Dependent Claim
45 words
The microprocessor according to claim 7, wherein the external signal input into said input buffer is an address signal, said logic circuit is an address decoder whose logic element at least a primary stage is disposed in said passway where said input buffer is provided.
References Cited (Backward Citations)
US4954987A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |