Contacting integrated circuit chip terminal through the wafer kerf

Claim 2

In the testing of a monolithic integrated semiconductor circuit structure wherein each of a plurality of integrated circuits are formed on one of a plurality of chips on a wafer, said chips being separated by a wafer kerf, a method for externally accessing mechanically difficult to access chip terminals by a tester comprising forming in said kerf, a test circuit comprising at least one externally accessible circuit terminal, at least one conductive bus bar connected to said at least one kerf terminal, and connecting means for connecting each of a plurality of chip terminals on a plurality of chips to said conductive bus bar, said connecting means being normally inactive, connecting a tester to said kerf terminal, selectively activating said connecting means to provide conductive signal paths from selected chip terminals to said kerf terminal, and dicing the wafer into the discrete chips by removing the kerf.

Claim 3

The testing method of claim 1 wheRein said connecting means are selectively activated by selectively activating the chips on which the selected terminals are located.

Claim 4

The method of claim 2 wherein said chips are arranged in an array of rows and columns, and said connecting means include a plurality of gating circuits formed in said kerf, each of which circuits is associated with a respective one of said chips and is adapted to activate said associated chip upon the application of a pair of signals to said gating circuit, a plurality of gate input connectors formed in said kerf, each of which is respectively connected to all of the gating circuits associated with a row or column of chips, and said selective activation is carried out by means for selectively applying a first signal to the input connectors for gating circuits associated with a selected row of chips and for selectively applying a second signal to the input connections for gating circuits associated with a selected column of chips whereby one gating circuit associated with the chip to be selectively activated will have the requisite pair of signals applied thereto.

Claim 5

The method of claim 2 wherein said test circuit comprises a plurality of kerf terminals and a corresponding plurality of conductive bus bars connected thereto, said bus bars being metal.

Claim 6

The method of claim 2 wherein said test circuit comprises a plurality of kerf terminals and a corresponding plurality of conductive bus bars connected thereto, said bus bars being low conductivity diffused semiconductor regions formed in said kerf.