Controller for peripheral data storage units

Claim 1

In a data processing system having a central processing unit and a plurality of peripheral data storage units, said peripheral units employing disparate operating control signals and operating at disparate characteristic data signal processing frequencies, said central processing unit providing read, write, format, and storage unit select control signals, a controller connected to said central processing unit and to said peripheral data storage units, and configured to transfer, in response to control signals from said central processing unit, data signals between said central processing unit and any of said peripheral storage units, said controller including temporary data storage means for holding data signals temporarily, while being transferred between said central processor and any of said peripheral storage units, means for transferring data signals between said temporary data storage means and any of said peripheral units or said central processing unit, instruction storage means for storing instructions for read, write, and format operations effecting transfer of data between said temporary storage unit and said peripheral storage units, selection and addressing means for providing selected address signals to said instruction storage means, operating circuitry means for providing signals to control said peripheral data storage units, instruction register means for receiving instructions from said instruction storage means and providing selected input signals to said operating circuitry means, timing means for providing periodic timing signals controlling the rate of processing of sequential instructions, wherein instructions stored in said instruction storage means are stored in blocks of contiguous addresses, each block containing exclusively the instructions for carrying out a read, write, or format function for a specific peripheral unit, the instructions within each block being stored at addresses in a sequential order corresponding without exception to the temporal order of implementing the instructions for the function and peripheral unit corresponding to the block, said selection and addressing means transmits in response to a signal from said central processor a sequence of address signals to said instruction storage unit beginning with an initial address selected in accordance with said read, write, format, and storage unit select control signals, said initial address being the first address of the block of contiguous addresses relating to the function specified by the read, write, and unit select control signals, and said timing means includes means responsive to said control signals provided by said central processing unit and specifying a particular one of said peripheral units and a particular one of said functions for selecting periodic timing signals repeated at the characteristic rate of operation of any of said peripheral units, said timing signals being applied to increment the current instruction of the instruction register.