US4379327A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Universal interface circuit for synchronous and asynchronous buses
Assignee: Motorola Solutions Inc
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Filing: 1980-07-21
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Granted: 1983-04-05
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Expires: 2000-07-21
Abstract
Abstract A universal bus interface circuit can be used in conjunction with either synchronous or asynchronous bus systems. An input terminal is monitored to determine if the bus is synchronous or asynchronous. If the bus is asynchronous, a synchronization circuit generates a synchronous control signal for internal use from an asynchronous select signal. The synchronization circuit also generates an asynchronous hand-shake or acknowledge signal which is applied to the input terminal to indicate completion of the operation. The input terminal is monitored by a host processor.
Inventors
- 👤 Donald Tietjen
- 👤 Sharon Lamb
- 👤 Pern Shaw
- 👤 Duane Cawthron
- 👤 Paul D. Shannon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
82 words
An interface circuit for use in conjunction with a data processing system bus, comprising: first means coupled to said bus for receiving a select signal from said data processing system; second means for receiving an indication as to whether said bus is synchronous or asynchronous; third means coupled to said first means for passing said select signal if said bus is synchronous; and fourth means coupled to said first and second means for synchronizing said select signal if said bus is asynchronous.
Claim 2
Dependent Claim
82 words
An interface circuit for use in conjunction with a data processing system bus, comprising: first means coupled to said bus for receiving a select signal from said data processing system; second means for receiving an indication as to whether said bus is synchronous or asynchronous; third means coupled to said first means for passing said select signal if said bus is synchronous; and fourth means coupled to said first and second means for synchronizing said select signal if said bus is asynchronous.
Claim 3
Dependent Claim
33 words
A circuit according to claim 1 further including fifth means coupled to said fourth means for applying an acknowledge signal to said first means to indicate the completion of an asynchronous bus operation.
Claim 4
Dependent Claim
49 words
A circuit according to claim 2 wherein said data processing system terminates said select signal in response to said acknowledge signal and wherein said circuit further includes sixth means coupled to said first and second means for pulsing said second means in response to termination of said select signal.
Claim 5
Dependent Claim
36 words
A circuit according to claim 3 wherein said second means further includes latching means for storing said indication and for generating a first signal for synchronous bus operation and a second signal for asynchronous bus operation.
Claim 6
Dependent Claim
141 words
An interface circuit for interacting with the bus of a microprocessor system, comprising: first terminal means coupled to said bus for receiving a select signal from said microprocessor; second terminal means coupled to said bus for receiving an indication as to whether said bus is synchronous or asynchronous; latching means coupled to said second terminal means for generating a first signal if the bus is synchronous and a second signal if said bus is asynchronous; third means coupled to said first and second terminal means and responsive to said second signal for synchronizing said select signal; fourth means coupled to said first terminal means and responsive to said first signal for passing said select signal; and fifth means coupled to said third means for placing an acknowledge signal on said second terminal means after an asynchronous bus operation has been completed.
Claim 7
Dependent Claim
141 words
An interface circuit for interacting with the bus of a microprocessor system, comprising: first terminal means coupled to said bus for receiving a select signal from said microprocessor; second terminal means coupled to said bus for receiving an indication as to whether said bus is synchronous or asynchronous; latching means coupled to said second terminal means for generating a first signal if the bus is synchronous and a second signal if said bus is asynchronous; third means coupled to said first and second terminal means and responsive to said second signal for synchronizing said select signal; fourth means coupled to said first terminal means and responsive to said first signal for passing said select signal; and fifth means coupled to said third means for placing an acknowledge signal on said second terminal means after an asynchronous bus operation has been completed.
Claim 8
Dependent Claim
50 words
A circuit according to claim 5 wherein said microprocessor terminates said select signal in response to said acknowledge signal and wherein said circuit further includes sixth means coupled to said first and second terminal means for pulsing said second terminal means in response to the termination of said select signal.
Claim 9
Dependent Claim
28 words
A circuit according to claim 6 further including reset means coupled to said third and fifth means for initializing said circuit in the absence of said select signal.
References Cited (Backward Citations)
US3999163A
Cited
US4215243A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-04 | 1986-10-04 | 1987-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-04 | 1990-10-04 | 1991-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-04 | 1994-10-04 | 1995-04-05 | $7700.00 | Window Closed / Lapsed |