Reprogrammable control circuit

Claim 2

An integrated circuit comprising: a bit shift register for serially receiving and storing a serial bit signal, and having a control output signal; said control signal represents the state of the serial input bit signal stored in said register; and a transmission gate means for receiving an input signal and said control signal and having an output signal, said transmission gate means for transmitting said input signal to said output signal as controlled by said control signal.

Claim 3

The circuit of claim 1 further comprising: a plurality of bit shift registers, each bit register having a serial output bit signal and receiving a serial input bit signal from the serial output bit signal of another shift register; and a plurality of transmission gate means each gate means being controlled by one serial bit shift register.

Claim 4

The circuit of claim 2 wherein each transmission gate means is an AND gate, NOR gate, NAND gate or Exclusive OR gate.

Claim 5

The circuit of claim 2 wherein each transmission gate means is a transmission gate.

Claim 6

The circuit of claim 2 comprising: a first array of logic gates, said first array having a plurality of inputs and a plurality of outputs; and outputs signals of said transmissions gate means are supplied to the inputs of said first array.

Claim 7

The circuit of claim 5 further comprising: a second array of logic gates, said second array having a plurality of inputs and a plurality of outputs; output signals of said transmission gate means are supplied to the inputs of said second array; and said first array and said second array have substantially the same physical shape.

Claim 8

The circuit of claim 6 wherein each of said arrays of logic gates and transmission gate means is substantially in the physical shape of a hexagon.

Claim 9

The circuit of claim 6 wherein each of said arrays of logic gates and transmission gate means is substantially in the physical shape of a right triangle and wherein two said arrays of logic gates and transmission gate means are positioned to form a rectangle.

Claim 10

The circuit of claim 5 wherein said first array further comprises: a plurality of groups of logical AND gates; a plurality of logical OR gates; and the output of each AND gate is connected to the input of a logical OR gate.

Claim 11

The circuit of claim 9 wherein each logical AND gate is programmably connected to an input of more than one logical OR gate.

Claim 12

The circuit of claim 10 further comprising: a second plurality of bit shift registers, each for serially receiving and storing a serial input bit signal and having a serial output bit signal and a control signal, the serial input bit signal connected to the serial output bit signal of another bit shift register; said control signal is the stored serial input bit signal in said serial bit shift register; and a plurality of transmission gate means, each gate means being controlled with a bit shift register and for transmitting an output of the first plurality of AND gates to an input of an OR gate in the second plurality as controlled by said control signal of the bit shift register.

Claim 13

The circuit of claim 5 wherein said first array further comprises: a plurality of groups of logical NOR gates; a second plurality of logical NOR gates; the output of a NOR gate of the first plurality of NOR gates is connected to an input of a NOR gate of the second plurality of NOR gates.

Claim 14

The circuit of claim 12 wherein each input of said array is programmably connected to an input of a NOR gate of the first plurality of NOR gates.

Claim 15

The circuit of claim 12 wherein each output of each of logical NOR gates of the first plurality of NOR gates is programmably connected to an input of more than one logical NOR gate of the second plurality of NOR gates.

Claim 16

The circuit of claim 14 further comprising: a second plurality of bit shift registers, each for serially receiving and storing a serial bit signal and having a serial output bit signal and a control signal, the serial input bit signal connected to the serial output bit signal of another bit shift register; said control signal is the stored state of serial input bit signal in said bit shift register; and a plurality of transmission gate means, each gate means being controlled by a bit shift register and for transmitting the output of a NOR gate of the first plurality of NOR gates to an input of a NOR gate in the second plurality as controlled by said control signal.

Claim 17

The circuit of claim 15 further comprising: a plurality of logical exclusive OR gates, each having two inputs and one output and a plurality of serial bit shift registers, for serially receiving and storing a serial bit signal, having a control output signal and having a serial output bit signal; said control signal represents the state of the serial input bit signal stored in said register; one input of each exclusive OR gate is the output of a NOR gate of the first plurality of NOR gates, the other input of that exclusive OR gate is the control output signal of a serial bit shift register; a plurality of transmission gate means, each transmission gate means of the third plurality controlled by a serial bit shift register of the third plurality of serial bit shift registers; said control signal generated by the bit shift register is the state of the serial input bit signal stored in said register; the control signals of a bit shift register is connected to the control input of the transmission gate means; the input of the transmission gate means is connected to the output of a NOR gate of the first plurality of NOR gates; the output of the transmission gate means is connected to the input of a NOR gate of the second plurality of NOR gates as controlled by said control signal.

Claim 18

The circuit of claim 2 further comprising: a read/write memory having a plurality of input address lines and a plurality of data lines; each output signal of a transmission gate means of the first group is connected to an input address line and each output signal of a transmission gate means of the second group is connected to a data line; and each input signal of each transmission gate means of the first group provides the input address to said memory and each transmission gate means of the second group controlling the data to and from said memory.

Claim 19

The circuit of claim 2 wherein the output signal of all transmission gate means are connected together and where said plurality of transmission gate means comprises two groups, a first group and a second group, each of said first group of transmission gate means for receiving a signal of a row as its input signal, and each of said second group of transmission gate means for receiving a signal of a column as its input signal.

Claim 20

The circuit of claim 2 further comprising: a processor having a plurality of input lines including clock, operand and carry-in, and a plurality of output lines including data and carry-out; each output signal of a transmission gate means of the first group is connected to an input line and each input signal of a transmission gate means of the second group is connected to an output line; and each input signal of each transmission gate means of the first group provides the input to said processor and each output signal of each transmission gate means of the second group provides an output of said processor.

Claim 21

The circuit 19 further comprising: a plurality of processors, each having a plurality of input lines and a plurality of output lines.

Claim 22

The circuit 19 further comprising: a plurality of processors, each having a plurality of input lines and a plurality of output lines.

Claim 23

The circuit of claim 2 further comprising: a counter having a plurality of inputs lines including data, set, pulse, count up, and count down and a plurality of output lines including carry up and carry down and data-out; each input signal of a transmission gate means of the first group is connected to an input line and each input signal of a transmission gate means of the second group is connected to an output line; and each output signal of each transmission gate means of the first group provides an input to said counter, and each output signal of each transmission gate means of the second group provides an output of said counter.

Claim 24

The circuit of claim 20 further comprising: a plurality of counters with the output signal of some of the transmission gate means of the second group connected to another counter.

Claim 25

The circuit of claim 2 further comprising: a content addressable memory, having data input lines, data output lines, address input lines, result output lines and result input lines; an input data bus comprising a plurality of input lines; an output data bus comprising a plurality of output lines; an address bus comprising a plurality of address lines; a first group of a plurality of transmission gate means, each having an input signal connected to said input data bus and an output signal connected to said data input lines; a second group of a plurality of transmission gate means, each having an input signal connected to said address bus and an output signal connected to said address input lines; and a third group of a plurality of transmission gate means, each having an input signal connected to said data output lines and an output signal connected to said output data bus.

Claim 26

The circuit of claim 23 further comprising: a plurality of content addressable memories and a fourth group of transmission gate means, each having an input connected to a result output line of one content addressable memory word and an output signal connected to a result input line of another content addressable memory word; a serial bit shift register whose control output is connected to the control input of each transmission gate means of the fourth plurality of transmission gate means.

Claim 27

The circuit of claim 2 further comprising: an N input to 2 N output demultiplexer; the outputs of said transmission gate means are connected to the inputs of the N input to 2 N output demultiplexer; a plurality of flip-flops, each having a data input and an output; for each of the flip-flops in said plurality, there is a transmission gate means for receiving a logic signal whose control input is connected to one of the 2 N outputs of the demultiplexer and whose output is connected to the data input of the flip-flop; and for each of the flip-flops in said plurality, there is a transmission gate means whose control input is connected to an output of the 2 N demultiplexer, and whose input is connected to the output of the flip-flop, whereby one of the outputs of the demultiplexer controls the output of the flip-flop.

Claim 28

The circuit of claim 2 further comprising: a first group of bit shift registers and an associated transmission gate means, and a second group of bit shift registers and an associated transmission gate means; means for connecting the output signal of a plurality of transmission gate means of the first group to the serial bit signal of the bit shift registers of the second group; means for connecting the input signal of a plurality of transmission gate means of the first group to the serial output bit signal of the bit shift registers of the second group; whereby serial input bit signals stored in the shift registers of the first group act to connect certain serial input signals of the shift registers of the second plurality to certain serial output signals of the shift registers of the second group.