US5128737A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit fabrication yield improvements
Assignee: Silicon Dynamics Inc
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Filing: 1990-03-02
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Granted: 1992-07-07
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Expires: 2010-03-02
Abstract
Abstract Microelectronic integrated circuit fabrication yield is improved through architecture which provides for the search and identification and avoidance of electronic malfunctions in wafer sub-circuits, each of which perform an identical function, such as memory. A processor contained within each wafer performs these search, identification and repair functions via communication pathways (busses) formed on the wafer. The processor records the location and type of electronic defects within each sub-circuit and reconfigures the balance of the circuitry included within the overall circuit to provide for a useful overall electronic circuit function using the sub-circuit building blocks.
Inventors
- 👤 Leonard A. van der Have
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:31
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W72/00; H10W72/50; H10W72/541; H10W72/5445; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
271 words
A wafer interconnect system for distribution of power to circuits or devices fabricated on said wafer and for interconnecting said circuits comprising: a) a wafer substrate; b) an active device layer formed on said substrate upon which regions of devices are formed; c) a first patterned insulator layer formed over said device layer; d) a first patterned conductive layer formed over said first insulator layer with a first set of contacts extending between said first conductive layer and device layer for interconnecting devices in said active device layer via said first conductive layer; e) a second patterned insulator layer formed over said first conductor layer; f) a second patterned conductive layer formed over said second insulator layer with a second set of contacts extending between said second conductive layer and device layer for interconnecting devices in said active device layer via said second conductive layer; g) a third patterned insulator layer formed over said second conductive layer; h) a third substantially unpatterned conductive layer formed over said third insulator layer for applying a common voltage to a plurality of a third set of contacts coupled to said device layer; i) a protective layer formed over said third conductive layer; and j) an insulator formed between said active device layer and said substrate and resistance regions formed in said active device layer and extending through said insulator on one side and to one or more of said contacts on another side and wherein one or more of the resistance regions is contiguous with the substrate and the substrate is doped to be highly conductive for coupling power to the contiguous resistance regions.
Claim 2
Dependent Claim
271 words
A wafer interconnect system for distribution of power to circuits or devices fabricated on said wafer and for interconnecting said circuits comprising: a) a wafer substrate; b) an active device layer formed on said substrate upon which regions of devices are formed; c) a first patterned insulator layer formed over said device layer; d) a first patterned conductive layer formed over said first insulator layer with a first set of contacts extending between said first conductive layer and device layer for interconnecting devices in said active device layer via said first conductive layer; e) a second patterned insulator layer formed over said first conductor layer; f) a second patterned conductive layer formed over said second insulator layer with a second set of contacts extending between said second conductive layer and device layer for interconnecting devices in said active device layer via said second conductive layer; g) a third patterned insulator layer formed over said second conductive layer; h) a third substantially unpatterned conductive layer formed over said third insulator layer for applying a common voltage to a plurality of a third set of contacts coupled to said device layer; i) a protective layer formed over said third conductive layer; and j) an insulator formed between said active device layer and said substrate and resistance regions formed in said active device layer and extending through said insulator on one side and to one or more of said contacts on another side and wherein one or more of the resistance regions is contiguous with the substrate and the substrate is doped to be highly conductive for coupling power to the contiguous resistance regions.
Claim 3
Dependent Claim
65 words
The system of claim 1 wherein the resistance of said regions is low enough to provide current flow to operate the devices in the active device layer to which the resistance regions are connected, yet high enough to not impair operation of portions of the wafer interconnect system other than where the devices are located should the resistance region become connected to such other portions.
Claim 4
Dependent Claim
20 words
The system of claim 2 wherein the bulk resistivity of the substrate is between about 0.005 Ohm-centimeter and 0.1 Ohm-centimeter.
Claim 5
Dependent Claim
23 words
The system of claim 1 wherein the conductive layers are formed of metals taken from the group consisting of aluminum, copper and gold.
Claim 6
Dependent Claim
14 words
The system of claim 1 wherein the conductive layers are formed of doped polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |