Associative interconnection circuit

Abstract

Abstract The disclosed apparatus uses an associative memory technique for the selective coupling of circuit elements to a data bus wherein each element is assigned an associative address and is coupled to the data bus when it receives said address on its address lines. The apparatus further comprises a reconfiguration control unit for assigning associative addresses to all elements, allowing said elements to be addressed at random. When one function element is to be substituted for another, the reconfiguration control unit assigns the address of the replaced element to the replacing element. In this way, the user continues to use the same address, making an element replacement transparent to the user, thereby avoiding reprogramming by the user. In the preferred embodiment the associative address is stored in nonvolatile memory so that it will not be lost when power is turned off, but is electrically reprogrammable if necessary or desired. Power to each element may also be supplied through a bus line so that when the element is not addressed or is uncoupled, the power is disconnected, reducing the drive current required to operate an array of circuit elements. This technique is especially useful for wafer scale integration where a plurality of functional elements are contained on one wafer. The control unit can test the elements, designate some of the operable elements for use and designate the remaining operable elements as spares. Upon the failure of an element which is being used, the control unit can assign an unused address to the original element and the original address to the replacement element. Thus, the capability of random sparing of function elements can be accomplished on a single wafer in a way that is transparent to the user.

Inventors

• 👤 Yukun Hsia

Bibliographic Details