US3644906A
Expired / Lapsed
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Hybrid associative memory
Assignee: International Business Machines Corp
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Filing: 1969-12-24
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Granted: 1972-02-22
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Expires: 1989-12-24
Abstract
Abstract A memory is disclosed in which words are located by both associative and nonassociative addressing. The nonassociative portion of the address defines a general category for the word being searched and a corresponding portion of the memory. The associative portion of the address is searched within the addressed portion of the memory without regard to the actual memory location. Conventional nonassociative storage cell arrays are arranged to be addressed as an associative memory of threestate storage cells.
Inventors
- 👤 Arnold Weinberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:45
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
An associative memory comprising, a plurality of arrays of binary storage circuits each addressable nonassociatively by an address of n bits, each array representing a predetermined bit position of the memory, first means providing an address of n- 1 bits that represent a predetermined data category in which a search is to take place and define in a corresponding position of each array a storage cell formed of two binary storage circuits, second means providing for each memory bit position an additional bit for associative addressing, and third means responsive to said n- 1 bits and to the additional bit for each bit position to address a selected one of said binary circuits of each cell for a search operation, and fourth means interconnecting said arrays for detecting match and mismatch conditions of addressed words during a search.
Claim 2
Dependent Claim
138 words
An associative memory comprising, a plurality of arrays of binary storage circuits each addressable nonassociatively by an address of n bits, each array representing a predetermined bit position of the memory, first means providing an address of n- 1 bits that represent a predetermined data category in which a search is to take place and define in a corresponding position of each array a storage cell formed of two binary storage circuits, second means providing for each memory bit position an additional bit for associative addressing, and third means responsive to said n- 1 bits and to the additional bit for each bit position to address a selected one of said binary circuits of each cell for a search operation, and fourth means interconnecting said arrays for detecting match and mismatch conditions of addressed words during a search.
Claim 3
Dependent Claim
31 words
The associative memory of claim 1 including a mask register and wherein said third means includes means responsive to said mask register to inhibit a search operation on the corresponding array.
Claim 4
Dependent Claim
91 words
The associative memory of claim 2 wherein said third means comprises, a first decoder and a second decoder common to all said arrays and connected to decode said n- 1 bits provided by said first means, means connecting the outputs of said first decoder to corresponding points on each said array, means for each array responsive to said second means and to said mask register for gating said output of said second decoder to one or the other of a pair of binary storage circuits defined by said n- 1 bits.
Claim 5
Dependent Claim
27 words
The associative memory of claim 3 wherein said first and second means comprise a common register connected to receive a word to be searched in the memory.
Claim 6
Dependent Claim
21 words
The associative memory of claim 2 in which said third means includes an n-bit decoder formed integrally with the associated array.
Claim 7
Dependent Claim
28 words
The associative memory of claim 5 including pluralities of arrays for each bit position and a plurality of fourth means for groups of arrays forming a data word.
Claim 8
Independent Claim
106 words
A method of associatively operating a plurality of nonassociative arrays of binary storage elements, each array having an individual address decoder for an address of n bits and representing a predetermined bit position in a memory word, comprising, supplying to each said decoder n- 1 common address bits defining in each said array a storage cell made up of two binary storage elements and defining a data category to be searched within the memory, forming a predetermined additional address bit individual to each bit position from a corresponding bit of a search word, and supplying said additional bits to said decoders with said common address bits.
Claim 9
Independent Claim
106 words
A method of associatively operating a plurality of nonassociative arrays of binary storage elements, each array having an individual address decoder for an address of n bits and representing a predetermined bit position in a memory word, comprising, supplying to each said decoder n- 1 common address bits defining in each said array a storage cell made up of two binary storage elements and defining a data category to be searched within the memory, forming a predetermined additional address bit individual to each bit position from a corresponding bit of a search word, and supplying said additional bits to said decoders with said common address bits.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-21 | 1975-08-23 | 1976-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-21 | 1979-08-23 | 1980-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-21 | 1983-08-23 | 1984-02-22 | $7700.00 | Window Closed / Lapsed |