Semiconductor device using standard cell system

Claim 1

A semiconductor device comprising: a plurality of standard cells; a first array, arranged in a first direction, having some of the plurality of standard cells on a common level; a second array, arranged in the first direction adjacent to the first array, having others of the plurality of standard cells on the common level; first and second power lines implemented by a first conductive layer on a second level above the standard cells and extending in the first direction, for operating the standard cells; a first wiring implemented by a second conductive layer on a third level above the first conductive layer, extending in a second direction perpendicular to the first direction, the first wiring including a plurality of wires having a common length, each wire corresponding to an input/output terminal of a standard cell; a second wiring, entirely disposed over the first array, implemented by a third conductive layer above the second conductive layer, extending in the first direction, and connected to the first wiring; a third wiring, entirely disposed over the second array, implemented by the third conductive layer, extending in the first direction, and connected to the first wiring; and a fourth wiring implemented by a fourth conductive layer above the third conductive layer, extending in the second direction, and connected to the first wiring at connection portions entirely disposed over the first and second arrays.