Semiconductor memory device having information indicative of presence of defective memory cells

Claim 2

A semiconductor memory device storing data having a unit of N bits (N is an integer), characterized by comprising: M memory elements (1) (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data; M internal bus lines (2; BUS1 - BUS36) each carrying one-bit data and connected to a corresponding one of said M memory elements; designating means (3; 23), coupled to said M memory elements, for receiving an address signal (ADD) from an external device and for designating one of said plurality of blocks of each of said M memory elements so that M blocks are designated by said address signal; memory means (24a, 24a₁, 24a₂, 24a₃) for storing information on whether or not each of said plurality of blocks of each of said M memory elements has a defective memory cell and for outputting said information in accordance with said address signal; N external bus lines (4; 25; B1 - B32) each carrying one-bit data; and bus line switching means (5, 6; 20, 24, 24a; SW1 - SW32), provided between said M internal bus lines and N external bus lines and connected to said memory means, for determining whether each of said M blocks designated by said designating means has a defective memory cell by referring to said information from said memory means and for selectively connecting N internal bus lines among said M internal bus lines to said N external bus lines so that one of said M blocks which has a defective memory cell is prevented from being selected and another one of said M blocks is selected.

Claim 3

A semiconductor memory device as claimed in claim 1, characterized in that said bus line switching means (5, 6; 20, 24; SW1 - SW32) comprises N switches (SW1 - SW32) each connected between L (L is an integer and L < N < M) internal bus lines among said M internal bus lines and one of said N external bus lines, each of said N switches connecting one of said L internal bus lines to said one of said N external bus lines in accordance with said information supplied from said memory means (24a; 24a₁, 24a₂, 24a₃).

Claim 4

A semiconductor memory device as claimed in claim 2, characterized in that said information stored in said memory means (24a; 24a₁, 24a₂, 24a₃) includes control data indicating which one of said L internal bus lines is to be selected on the basis of whether or not each of said M memory blocks of each of said M memory elements (1) has a defective memory cell.

Claim 5

A semiconductor memory device as claimed in claim 2, characterized in that each of said switches (SW1 - SW32) has L input terminals (0 - 4) to which said L internal bus lines are connected, and said L internal bus lines are adjacent to each other.

Claim 6

A semiconductor memory device as claimed in claim 4, characterized in that said control data includes N numerical data pieces provided for every M blocks and corresponding to said N external bus lines, and when each of said N numerical data pieces related to a corresponding one of said N external bus lines (B1 - B32) indicates which one of said L input terminals is to be connected to said corresponding one of said N external bus lines.

Claim 7

A semiconductor memory device as claimed in claim 5, characterized in that said memory means (24a; 24a₁, 24a₂, 24a₃) has storage areas provided for said N numerical data pieces and in that when one of said storage areas of said memory means corresponding to an i-th external bus line (i = 1, 2, ...) of said N external bus line indicates a j-th input terminal (j = 0, 1, 2, ...) of said L input terminal, an i-th switch of said N switches which is connected to an i-th external bus line of said N external bus lines selects an (i + j)-th internal bus line of said M internal bus lines.

Claim 8

A semiconductor memory device as claimed in any of claims 1 to 6, characterized in that each of said M memory elements (1) has said plurality of blocks arranged into a matrix.

Claim 9

A semiconductor memory device as claimed in any of claims 1 to 7, characterized in that each of said M memory elements (1) is formed of a memory chip, and in that said semiconductor memory device comprises a printed circuit board on which said M memory elements are mounted.

Claim 10

A semiconductor memory device as claimed in any of claims 1 to 9, characterized in that each of said M memory elements is formed of an integrated circuit block, and in that said semiconductor memory device comprises a wafer-scale chip on which said M memory elements are formed.

Claim 11

A semiconductor memory device storing data having a unit of N bits (N is an integer), characterized by comprising: n x M memory elements (M(1, 1) - M(n, 36) (n is an integer, and M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data; M internal bus lines (BUS1 - BUS36) each carrying one-bit data and connected to corresponding n memory elements among said n x M memory elements so that said n x M memory elements are arranged into a matrix; designating means (23), coupled to said n x M memory elements, for receiving an address signal from an external device and for designating one of said plurality of blocks of each of said n x M memory elements so that M blocks are designated by said address signal; memory means (24a; 24a₁, 24a₂, 24a₃) for storing information on whether or not each of said plurality of blocks of each of said n x M memory elements has a defective memory cell and for outputting said information in accordance with said address signal; N external bus lines (25; B1 - B32) each carrying one-bit data; and bus line switching means (20, 24, 24a; SW1 - SW32), provided between said M internal bus lines and N external bus lines and connected to said memory means, for determining whether each of said M blocks designated by said designating means has a defective memory cell by referring to said information from said memory means and for selectively connecting N internal bus lines among said M internal bus lines to said N external bus lines so that one of said M blocks which has a defective memory cell is prevented from being selected and another one of said M blocks is selected.

Claim 12

A semiconductor memory device storing data having a unit of N bits (N is an integer), characterized by comprising: n x M memory elements (M(1, 1) - M(n, 36) (n is an integer, and M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data; M internal bus lines (BUS1 - BUS36) each carrying one-bit data and connected to corresponding n memory elements among said n x M memory elements so that said n x M memory elements are arranged into a matrix; designating means (23), coupled to said n x M memory elements, for receiving an address signal from an external device and for designating one of said plurality of blocks of each of said n x M memory elements so that M blocks are designated by said address signal; memory means (24a; 24a₁, 24a₂, 24a₃) for storing information on whether or not each of said plurality of blocks of each of said n x M memory elements has a defective memory cell and for outputting said information in accordance with said address signal; N external bus lines (25; B1 - B32) each carrying one-bit data; and bus line switching means (20, 24, 24a; SW1 - SW32), provided between said M internal bus lines and N external bus lines and connected to said memory means, for determining whether each of said M blocks designated by said designating means has a defective memory cell by referring to said information from said memory means and for selectively connecting N internal bus lines among said M internal bus lines to said N external bus lines so that one of said M blocks which has a defective memory cell is prevented from being selected and another one of said M blocks is selected.

Claim 13

A semiconductor memory device as claimed in claim 10, characterized in that said bus line switching means (20, 24, 24a; SW1 - SW32) comprises N switches (SW1 - SW32) each connected between L (L is an integer and L < N < M) internal bus lines among said M internal bus lines and one of said N external bus lines, each of said N switches connecting one of said L internal bus lines to said one of said N external bus lines in accordance with said information supplied from said memory means.

Claim 14

A semiconductor memory device as claimed in claim 11, characterized in that said information stored in said memory means (24a; 24a₁, 24a₂, 24a₃) includes control data (#1 - #32) indicating which one of said L internal bus lines is to be selected on the basis of whether or not each of said M memory blocks of each of said n x M memory elements (M(1, 1) - M(n, 32) has a defective memory cell.

Claim 15

A semiconductor memory device as claimed in claim 11, characterized in that each of said switches (24a; 24a₁, 24a₂, 24a₃) has L input terminals (0 - 4) to which said L internal bus lines are connected, and said L internal bus lines are adjacent to each other.

Claim 16

A semiconductor memory device as claimed in claim 13, characterized in that said control data (#1 - #32) includes N numerical data pieces provided for every M blocks and corresponding to said N external bus lines (B1 - B32), and each of said N numerical data pieces related to a corresponding one of said N external bus lines indicates which one of said L input terminals is to be connected to said corresponding one of said N external bus lines.

Claim 17

A semiconductor memory device as claimed in claim 14, characterized in that said memory means (24a; 24a₁, 24a₂, 24a₃) has storage areas provided for said N numerical data pieces and in that when one of said storage areas of said memory means corresponding to an i-th external bus line (i = 1, 2, ...) of said N external bus line (BUS1 - BUS36) indicates a j-th input terminal (j = 0, 1, 2, ...) of said L input terminal, an i-th switch of said N switches which is connected to an i-th external bus line of said N external bus lines (B1 - B32) selects an (i + j)-th internal bus line of said M internal bus lines.

Claim 18

A semiconductor memory device as claimed in any of claims 10 to 15, characterized in that each of said n x M memory elements (M(1, 1) - M(n, 32)) has said plurality of blocks arranged into a matrix.

Claim 19

A semiconductor memory device storing data having a unit of N bits (N is an integer), characterized by comprising: n x M memory elements (M(1, 1) - M(n, 32)) (n being an integer, and M being an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data; M internal bus lines (BUS1 - BUS36) each carrying one-bit data and connected to corresponding n memory elements among said n x M memory elements so that said n x M memory elements are arranged into a matrix; designating means (26), coupled to said n x M memory elements, for receiving an address signal (ADD) from an external device and for designating one of said plurality of blocks of each of said n x M memory elements so that M blocks are designated by said address signal; memory means (24a; 24a₁, 24a₂, 24a₃) for storing information on whether or not each of said plurality of blocks of each of said n x M memory elements has a defective memory cell and for outputting said information in accordance with said address signal; determining means (6; 63, 63a), connected to said memory means, for determining whether each of said M blocks designated by said designating means has a defective memory cell by referring to said information from said memory means and for outputting a control signal indicative of the results of the determination; serial data inputting means (60), coupled to said determining means, for receiving serial write data and for selectively outputting said serial write data bit by bit in accordance with said control signal from said determining means; serial/parallel converting means (61), connected to said M internal bus lines and said serial data inputting means, for converting said serial write data into parallel write data to be supplied to said M internal bus lines and for converting readout data from said M internal bus lines into serial readout data; and serial data outputting means (64), coupled to said determining means and said serial/parallel converting means, for selectively receiving said serial readout data bit by bit in accordance with said control signal from said determining means and for outputting said serial readout data to an external bus line (65) in serial form.

Claim 20

A semiconductor memory device storing data having a unit of N bits (N is an integer), characterized by comprising: n x M memory elements (M(1, 1) - M(n, 32)) (n being an integer, and M being an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data; M internal bus lines (BUS1 - BUS36) each carrying one-bit data and connected to corresponding n memory elements among said n x M memory elements so that said n x M memory elements are arranged into a matrix; designating means (26), coupled to said n x M memory elements, for receiving an address signal (ADD) from an external device and for designating one of said plurality of blocks of each of said n x M memory elements so that M blocks are designated by said address signal; memory means (24a; 24a₁, 24a₂, 24a₃) for storing information on whether or not each of said plurality of blocks of each of said n x M memory elements has a defective memory cell and for outputting said information in accordance with said address signal; determining means (6; 63, 63a), connected to said memory means, for determining whether each of said M blocks designated by said designating means has a defective memory cell by referring to said information from said memory means and for outputting a control signal indicative of the results of the determination; serial data inputting means (60), coupled to said determining means, for receiving serial write data and for selectively outputting said serial write data bit by bit in accordance with said control signal from said determining means; serial/parallel converting means (61), connected to said M internal bus lines and said serial data inputting means, for converting said serial write data into parallel write data to be supplied to said M internal bus lines and for converting readout data from said M internal bus lines into serial readout data; and serial data outputting means (64), coupled to said determining means and said serial/parallel converting means, for selectively receiving said serial readout data bit by bit in accordance with said control signal from said determining means and for outputting said serial readout data to an external bus line (65) in serial form.

Claim 21

A semiconductor memory device as claimed in claim 17, characterized in that said serial data inputting means (60) stops outputting said serial write data when said control signal shows that said serial write data is to be written into one of said M blocks which has a defective memory cell, and in that dummy data is written into said one of the M blocks instead of said serial write data.

Claim 22

A semiconductor memory device as claimed in claim 17 or claim 18, characterized in that said serial data outputting means (64) stops outputting said serial readout data when said control signal shows that said serial write data is read out from one of said M blocks which has a defective memory cell.

Claim 23

A semiconductor memory device as claimed in any of claims 17 to 19, characterized in that each of said n x M memory elements (M(1, 1) - M(n, 36)) has said plurality of blocks arranged into a matrix.