US5261077A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Configurable data path arrangement for resolving data type incompatibility
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-06-29
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Granted: 1993-11-09
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Expires: 2010-06-29
Abstract
Abstract Apparatus for sharing data between processors having certain incompatible data formats is provided. A configurable data path unit and an address mapping unit allow a peripheral processor to access addressable storage locations within a host processor's main memory and store data types in a format so that the both processors can correctly access and interpret the data.
Inventors
- 👤 James R. Duval
- 👤 Thomas E. Hunt
- 👤 Kevin R. Peterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:29
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/768; G06F12/00; G06F12/02; G06F12/04; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018; G06F13/4027; G06F13/404; G06F7/764
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
269 words
In a data processing system including a first processor coupled to a first bus, said first processor configured to issue a first address that identifies a predetermined location in a main memory for storing a plurality of data bytes in a first format, and a second processor coupled to the main memory via a second bus, said second processor configured to issue a second address that identifies that predetermined location in main memory such that said second processor may access those data bytes in a second format, apparatus for converting the data bytes from said first format to said second format comprising: a data path unit connecting said first bus to said second bus, said data path unit including first transceiver means for receiving the data bytes from said first bus in first positions of said first format and second transceiver means for transmitting the data bytes to said second bus in second positions of said second format for storage at the predetermined location in main memory; and a programmable mode register coupled to said first transceiver means and said second transceiver means via control line means, said programmable mode register having a first filed for storing format reconfiguration information used to control said first transceiver means and said second transceiver means such that the first positions of all of the data bytes received at said first transceivers may be transposed into the second positions at said second transceivers, thereby configuring said data path unit so that said second processor may access and correctly interpret the data bytes in said second format at the predetermined location in main memory.
Claim 2
Dependent Claim
269 words
In a data processing system including a first processor coupled to a first bus, said first processor configured to issue a first address that identifies a predetermined location in a main memory for storing a plurality of data bytes in a first format, and a second processor coupled to the main memory via a second bus, said second processor configured to issue a second address that identifies that predetermined location in main memory such that said second processor may access those data bytes in a second format, apparatus for converting the data bytes from said first format to said second format comprising: a data path unit connecting said first bus to said second bus, said data path unit including first transceiver means for receiving the data bytes from said first bus in first positions of said first format and second transceiver means for transmitting the data bytes to said second bus in second positions of said second format for storage at the predetermined location in main memory; and a programmable mode register coupled to said first transceiver means and said second transceiver means via control line means, said programmable mode register having a first filed for storing format reconfiguration information used to control said first transceiver means and said second transceiver means such that the first positions of all of the data bytes received at said first transceivers may be transposed into the second positions at said second transceivers, thereby configuring said data path unit so that said second processor may access and correctly interpret the data bytes in said second format at the predetermined location in main memory.
Claim 3
Dependent Claim
26 words
The apparatus of claim 1 wherein said programmable mode register is contained within an address mapping unit coupled between said first bus and said second bus.
Claim 4
Dependent Claim
29 words
The apparatus of claim 2 wherein said programmable mode register further includes a second field for storing address translation information for translating said first address to said second address.
Claim 5
Dependent Claim
14 words
The apparatus of claim 3 further comprising means for specifying said programmable mode register.
Claim 6
Dependent Claim
18 words
The apparatus of claim 4 wherein said means for specifying comprises a first field of said first address.
Claim 7
Dependent Claim
25 words
The apparatus of claim 5 wherein said address translation information is concatenated to a second field of said first address to generate said second address.
Claim 8
Dependent Claim
22 words
The apparatus of claim 6 wherein said format reconfiguration information stored in said programmable mode register is provided by an application program.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |