Self-correcting memory system

Claim 2

A memory system, comprising: a dynamic memory with a refresh cycle, said memory including a first memory portion for storing a plurality of data words and a second memory portion for storing groups of check bits, one group of check bits associated with each data word in said first memory portion; control circuitry for controlling the operation of said memory, including a refresh address counter for periodically supplying an address to said memory to refresh a block of the data words stored in said first memory portion; and error detection and correction means connected to said memory for periodically checking for and correcting any bit errors in each of the data words stored in said first memory portion, including a self-correct address counter augmenting said refresh address counter so that during each refresh cycle the address supplied to said memory defines a selected data word within the block refreshed, the selected data word being checked and corrected for any bit errors.

Claim 3

The memory system of claim 1, wherein said error detection and correction means further includes: first ECC generating means for receiving each data word to be stored in said first memory portion and generating a group of ECC check bits to be stored in said second memory portion; and ECC checking means for receiving such data word in said first memory portion and its associated group of ECC check bits in said second memory portion, said ECC checking means including second ECC generating means for generating a group of ECC bits in response to the received data word, and comparison means for comparing the ECC bits from said second ECC generating means and the ECC check bits from said second memory portion.

Claim 4

The memory system of claim 2, wherein said ECC checking means further includes means for generating a single bit error signal indicating any single bit error in the selected data word and the location of such single bit error in the selected data word, and wherein said error detection and correction means further includes bit correction means for receiving the selected data word and the single bit error signal and in response correcting the single bit error.

Claim 5

The memory system of claim 1, wherein said error detection and correction means further includes read/write signal generating means for generating a self-correct read signal to read the selected data word during each refresh cycle of said memory and a self-correct write signal to write the selected data word, including any corrected bit, back into said memory.

Claim 6

A memory system, comprising: a memory, including a first memory portion for storing a plurality of data words, and a second memory portion for storing groups of ECC check bits, one group of ECC check bits associated with each data word in said first memory portion; control circuitry for controlling the operation of said memory, including refresh address counter means for periodically supplying bits defining a block of data words in said first memory portion for being refreshed, said address bits being generated in response to a refresh request signal; first ECC generating means connected for receiving each data word to be stored in said first memory portion and in response generating a group of ECC check bits associated with the data word to be stored in said second memory portion; self-correct address counter means cascaded to said refresh address counter means to provide additional address bits for selected one data word in the block of data words being refreshed; self-correct read/write signal generating means connected to said memory, for generating a self-correct read signal to read the one selected data word and its associated group of check bits from said memory and generating a self-correct write signal for writing the one selected data word back into said memory; ECC checking means, including second ECC generating means connected for receiving the one selected data word from said first memory portion and in response generating ECC bits, Exclusive OR gate means connected for receiving and comparing the ECC check bits from said second memory portion associated with the one selected data word and the ECC bits generated by said second ECC generating means, and decode circuitry connected for receiving the output of said Exclusive OR gate means and in response generating a single bit error signal indicating the presence of a single bit error in the one selected data word; and bit correction means connected for receiving the single bit error signal from said decode circuitry and the one selected data word from said first memory portion and in response correcting any single bit error in the one selected data word.

Claim 7

A memory system, comprising: a memory, including a first memory portion for storing a plurality of data words, and a second memory portion for storing groups of ECC check bits, one group of ECC check bits associated with each data word in said first memory portion; control circuitry for controlling the operation of said memory, including refresh address counter means for periodically supplying bits defining a block of data words in said first memory portion for being refreshed, said address bits being generated in response to a refresh request signal; first ECC generating means connected for receiving each data word to be stored in said first memory portion and in response generating a group of ECC check bits associated with the data word to be stored in said second memory portion; self-correct address counter means cascaded to said refresh address counter means to provide additional address bits for selected one data word in the block of data words being refreshed; self-correct read/write signal generating means connected to said memory, for generating a self-correct read signal to read the one selected data word and its associated group of check bits from said memory and generating a self-correct write signal for writing the one selected data word back into said memory; ECC checking means, including second ECC generating means connected for receiving the one selected data word from said first memory portion and in response generating ECC bits, Exclusive OR gate means connected for receiving and comparing the ECC check bits from said second memory portion associated with the one selected data word and the ECC bits generated by said second ECC generating means, and decode circuitry connected for receiving the output of said Exclusive OR gate means and in response generating a single bit error signal indicating the presence of a single bit error in the one selected data word; and bit correction means connected for receiving the single bit error signal from said decode circuitry and the one selected data word from said first memory portion and in response correcting any single bit error in the one selected data word.