System for providing gapless data transfer from page-mode dynamic random access memories

Claim 2

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addressed to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; said memory controller including means for providing a Column Address Strobe (CAS) signal, said memory support circuitry further including means for changing said unique column addresses provided to each of said plurality of memory modules in response to a transition of said CAS signal.

Claim 3

The digital processing system as claimed in claim 1 wherein said memory controller incorporates programmable means to control the access time of said memory.

Claim 4

The digital processing system as claimed in claim 1 wherein said memory support circuitry includes a multiple word buffer, said multiple work buffer storing words from said plurality of memory modules, including said selected word, in response to said Column Address Strobe (CAS) signal.

Claim 5

The processing system of claim 3 wherein said memory support circuitry further includes fetch circuitry for transferring a word from said buffer to said interconnection network.

Claim 6

The processing system of claim 4 wherein said fetch circuitry includes means to transfer successive words from said multiple word buffer.

Claim 7

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules in the form of a plurality of dynamic random access memory modules which are accessed in page mode to obtain a line of data; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory support circuitry further includes means responsive to said first control signal for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data.

Claim 8

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules in the form of a plurality of dynamic random access memory modules which are accessed in page mode to obtain a line of data; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory support circuitry further includes means responsive to said first control signal for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data.

Claim 9

The digital processing system as claimed in claim 6 wherein the plurality of memory modules provide a memory bank, and wherein said memory controller multiplexes said first control signal with a bank select signal provided to select a subset of said plurality of memory modules with the bank select signal.

Claim 10

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory controller includes means for providing a Column Address Strobe (CAS) signal, said memory support circuitry further including means for changing said unique column addresses provided to each of said plurality of memory modules in response to a transition of said CAS signal and wherein said memory support circuitry further includes means responsive to said first control signal for steering a Column Address Strobe (CAS) signal to said plurality of memory modules associated with said line of data.

Claim 11

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory controller includes means for providing a Column Address Strobe (CAS) signal, said memory support circuitry further including means for changing said unique column addresses provided to each of said plurality of memory modules in response to a transition of said CAS signal and wherein said memory support circuitry further includes means responsive to said first control signal for steering a Column Address Strobe (CAS) signal to said plurality of memory modules associated with said line of data.

Claim 12

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules in the form of a plurality of dynamic random access memory modules which are accessed in page mode to obtain a line of data; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory support circuitry further includes means responsive to said control signal for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data, and wherein said memory controller further incorporates programmable means to control the access time of the memory.

Claim 13

A digital processing system comprising: a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules in the form of a plurality of dynamic random access memory modules which are accessed in page mode to obtain a line of data; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory support circuitry further includes means responsive to said control signal for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data, and wherein said memory controller further incorporates programmable means to control the access time of the memory.

Claim 14

A digital processing system comprising a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules in the form of a plurality of dynamic random access memory modules which are accessed in page mode to obtain a line of data; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory support circuitry further includes means responsive to said first control signal for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data; and wherein said memory controller further includes programmable circuitry for controlling generation of row and column timing signals for said dynamic random access memory modules, and for controlling generation of row and column addresses in support of page and non-page mode addressing of said dynamic random access memory modules.

Claim 15

A digital processing system comprising a digital processor; a memory organized in rows and columns and including memory support circuitry and a plurality of memory modules in the form of a plurality of dynamic random access memory modules which are accessed in page mode to obtain a line of data; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating a first control signal indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said memory support circuitry further includes means responsive to said first control signal for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data; and wherein said memory controller further includes programmable circuitry for controlling generation of row and column timing signals for said dynamic random access memory modules, and for controlling generation of row and column addresses in support of page and non-page mode addressing of said dynamic random access memory modules.

Claim 16

A digital processing system comprising a plurality of digital processor; a plurality of memories organized into rows and columns including memory support circuitry and a plurality of memory modules; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating first control signals indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said plurality of memories include a plurality of dynamic random access memory modules which are accessed in page mode by said memory support circuitry to obtain a line of data indicated by said first control signal; and wherein said memory controller includes means for providing a CAS signal and said memory support circuitry further includes means for changing the column address to the dynamic memory modules in response to an active to inactive transition of said CAS signal.

Claim 17

A digital processing system comprising a plurality of digital processor; a plurality of memories organized into rows and columns including memory support circuitry and a plurality of memory modules; an interconnection network including a memory controller coupled between said processor and said memory for sequencing the memory operations, said memory controller generating first control signals indicating a selected word of a line of data; and said memory support circuitry including means responsive to said first control signal for concurrently generating a unique column address for each of said plurality of memory modules and for providing said unique column addresses to each of said plurality of memory modules, said unique column addresses being a function of said first control signal and specifying the starting word and successive column addresses associated with successive words of the line of data in memory; and wherein said plurality of memories include a plurality of dynamic random access memory modules which are accessed in page mode by said memory support circuitry to obtain a line of data indicated by said first control signal; and wherein said memory controller includes means for providing a CAS signal and said memory support circuitry further includes means for changing the column address to the dynamic memory modules in response to an active to inactive transition of said CAS signal.

Claim 18

The processing system of claim 11 wherein said memory support circuitry further includes means responsive to said first control signals for steering a Column Address Strobe (CAS) signal to said dynamic random access modules associated with said line of data.

Claim 19

The digital processing system as claimed in claim 11 wherein said memory controller further includes programmable means to control access time of said memories.

Claim 20

The digital processing system as claimed in claim 11 wherein the plurality of memory modules provide a memory bank, and wherein said memory controller multiplexes said first control signal with a bank select signal provided to select a subset of said plurality of memory modules with the bank select signal.