US4653050A
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US
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Fault-tolerant memory system
Assignee: Northrop Grumman Corp
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Filing: 1984-12-03
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Granted: 1987-03-24
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Expires: 2004-12-03
Abstract
Abstract A semiconductor memory structure having multiple memory modules that can be assigned or reassigned to serve in different logical memory locations, to obviate fault conditions detected in one or more modules. A logical addressing scheme treats the memory as having P pages, each with N multibit memory words. The memory modules are each 1×N bits in size and each module provides one bit of memory at the same bit position in every word in the page. This minimizes the effect of radiation damage, since a damaged module will affect only one bit in each word, and one missing bit in a word can be reconstructed using conventional error detection and correction techniques. The memory structure includes a memory mapping unit, which yields a set of module assignments for each page of memory.
Inventors
- 👤 Steven Vaillancourt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G06; G06F; G06F11/00; G11C29/88; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
268 words
A memory circuit, addressable by a logical memory address that includes a memory page address and a memory word address within the specified page, the circuit comprising: a plurality of memory modules, each having as many memory elements as there are memory words in a memory page; memory module mapping means, for associating each combination of memory page and bit position within each data word on that page with a unique selected memory module; and means connected to the memory modules and to the memory module mapping means, for controlling data access to the memory modules such that a selected memory word in a selected memory page is distributed over a plurality of memory modules; wherein the memory modules are arranged in rows; wherein the memory module mapping means receives as input a logical page address, and supplies as outputs, to the means for controlling access to the memory modules, a set of module addresses and data word bit positions; wherein the means for controlling access to the memory modules includes multiplexing means for each row of modules, for selecting a data line for connection to the row of modules, and further includes module selection means for each row of modules; and wherein the memory mapping means includes means responsive to a page address for generating for each row of modules a module address for application to the module selection means, and a bit position address for application to the multiplexing means, whereby each memory page is mapped into a plurality of memory modules, each module serving as one bit position for all N words of the page.
Claim 2
Dependent Claim
268 words
A memory circuit, addressable by a logical memory address that includes a memory page address and a memory word address within the specified page, the circuit comprising: a plurality of memory modules, each having as many memory elements as there are memory words in a memory page; memory module mapping means, for associating each combination of memory page and bit position within each data word on that page with a unique selected memory module; and means connected to the memory modules and to the memory module mapping means, for controlling data access to the memory modules such that a selected memory word in a selected memory page is distributed over a plurality of memory modules; wherein the memory modules are arranged in rows; wherein the memory module mapping means receives as input a logical page address, and supplies as outputs, to the means for controlling access to the memory modules, a set of module addresses and data word bit positions; wherein the means for controlling access to the memory modules includes multiplexing means for each row of modules, for selecting a data line for connection to the row of modules, and further includes module selection means for each row of modules; and wherein the memory mapping means includes means responsive to a page address for generating for each row of modules a module address for application to the module selection means, and a bit position address for application to the multiplexing means, whereby each memory page is mapped into a plurality of memory modules, each module serving as one bit position for all N words of the page.
Claim 3
Dependent Claim
244 words
A memory circuit having excess capacity to be used in the event of the detection of defects, the circuit being addressable by a logical address that includes a page address and a word address within the selected page, the memory circuit comprising: a plurality of memory modules, each having N bits of memory, where N is the number of words in a page, the modules being arranged in R rows, where R is at least as great as the number of bit positions in each word, and the total number of modules exceeds the product of the number of pages P and the number of bit positions W in each word; a data bus for each row, coupled to all of the modules in the row; multiplexing means for each row of modules, for connection of a selected data line, corresponding to a selected bit position, to the data bus for the row; a module selection address bus for each row; a word address bus coupled to all of the modules to effect selection of a particular word within a page; memory mapping means, responsive to a page address, for generating R data bit position signals for application to the respective multiplexing means, and R module selection addresses for application to the module selection address bus, whereby the addressing of a specific page results in the selection of a predetermined set of memory modules, one for each data bit position in each memory words.
Claim 4
Dependent Claim
244 words
A memory circuit having excess capacity to be used in the event of the detection of defects, the circuit being addressable by a logical address that includes a page address and a word address within the selected page, the memory circuit comprising: a plurality of memory modules, each having N bits of memory, where N is the number of words in a page, the modules being arranged in R rows, where R is at least as great as the number of bit positions in each word, and the total number of modules exceeds the product of the number of pages P and the number of bit positions W in each word; a data bus for each row, coupled to all of the modules in the row; multiplexing means for each row of modules, for connection of a selected data line, corresponding to a selected bit position, to the data bus for the row; a module selection address bus for each row; a word address bus coupled to all of the modules to effect selection of a particular word within a page; memory mapping means, responsive to a page address, for generating R data bit position signals for application to the respective multiplexing means, and R module selection addresses for application to the module selection address bus, whereby the addressing of a specific page results in the selection of a predetermined set of memory modules, one for each data bit position in each memory words.
Claim 5
Dependent Claim
118 words
A memory circuit as set forth in claim 2, wherein the memory mapping means includes: a page address decoder, for generating a page selection signal on one of P selection lines; a look-up table having P rows, each with R entries, each entry having a module selection field and a data bit selection field, and each row being enabled for access by a separate one of the P selection lines; means for gating the contents of each module selection field onto the module selection address bus for the row of modules with which it is associated; and means for transmitting the contents of each data bit selection field to the appropriate multiplexing means in each row of modules.
Claim 6
Dependent Claim
54 words
A memory circuit as set forth in claim 2, wherein each memory module includes: module selection means, responsive to signals on the module selection bus, to select the module for data transfer; and cell addressing means, responsive to signals on the word address bus, to select a cell within the module for data transfer.
Claim 7
Dependent Claim
42 words
A memory circuit as set forth in claim 4, wherein: the module selection means includes a comparator and a storage register to hold a module address; and the cell addressing means includes a decoder for decoding signals from the word address bus.
Claim 8
Dependent Claim
54 words
A memory circuit as set forth in claim 3, wherein each memory module includes: module selection means, responsive to signals on the module selection bus, to select the module for data transfer; and cell addressing means, responsive to signals on the word address bus, to select a cell within the module for data transfer.
Claim 9
Dependent Claim
42 words
A memory circuit as set forth in claim 6, wherein: the module selection means includes a comparator and a storage register to hold a module address; and the cell addressing means includes a decoder for decoding signals from the word address bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |