Memory with reconfiguration to avoid uncorrectable errors

Claim 2

A memory comprising, interchangeable modular units of storage cells, the cells of each of said units being associated with particular bit positions of the memory such that a memory word is formed of storage cells in a plurality of units, means providing a multibit address for selecting a word location in said units for a memory operation, and means providing a plurality of unique logic functions of said address to said units for defining as a word location, cells differently located in said units having different logic functions of said address, whereby interchanging said units having different functions of said address provides a reconfiguration of the storage cells forming said word locations.

Claim 3

A memory of the type having storage cells packaged in replaceable units, means for correcting a limited number of errors in a word location without replacing a unit, means for detecting but not correcting a greater number of errors in a word location, and means connected to each said replaceable unit for supplying signals to select storage cells forming a word location, wherein the improvement comprises, means providing a unique address relationship between a plurality of said replaceable units and said signals, whereby interchanging a unit having a defective storage cell in a word location having detectable but uncorrectable errors with another unit of the memory having a different address relationship produces a reconfiguration of the storage cells in a plurality of word locations for changing uncorrectable multiple errors to correctable errors.

Claim 4

A memory of the type having storage cells packaged in replaceable units, means for correcting a limited number of errors in a word location without replacing a unit, means for detecting but not correcting a greater number of errors in a word location, and means connected to each said replaceable unit for supplying signals to select storage cells forming a word location, wherein the improvement comprises, means providing a unique address relationship between a plurality of said replaceable units and said signals, whereby interchanging a unit having a defective storage cell in a word location having detectable but uncorrectable errors with another unit of the memory having a different address relationship produces a reconfiguration of the storage cells in a plurality of word locations for changing uncorrectable multiple errors to correctable errors.

Claim 5

The memory of claim 2 in which said means providing a unique addressing relationship comprises components of the memory addressing circuit differently connected at said plurality of replaceable units.

Claim 6

The memory of claim 2 in which said addressing components represent fewer than all of the addressing bits of said address.

Claim 7

The memory of claim 2 in which said addressing circuit components are wires carrying the true and complement values of selected bits of an address.

Claim 8

The memory of claim 5 in which said wires are connected in different permutations at each bit position.

Claim 11

A memory comprising, storage cells arranged to form bit positions of the memory, means providing a multibit address for selecting a word location of the memory, an address circuit interconnecting said bit positions in a configuration for a plurality of said bit positions to have storage cells of a word location differently positioned, and logic means in the addressing circuit connections to said bit positions to provide a selected logic function of saiD address to said bit positions.

Claim 12

A memory comprising, storage cells arranged to form bit positions of the memory, means providing a multibit address for selecting a word location of the memory, an address circuit interconnecting said bit positions in a configuration for a plurality of said bit positions to have storage cells of a word location differently positioned, and logic means in the addressing circuit connections to said bit positions to provide a selected logic function of saiD address to said bit positions.

Claim 13

The memory of claim 8 further including means for encoding a word to be stored in the memory in an error correction code and for decoding words read from the memory for correcting single bit errors and detecting double bit errors.

Claim 14

The memory of claim 9 wherein said address circuit comprises an address register for holding said address, an address decoder for each of said bit positions, and means connected between said address register and said address decoders for inverting selected bits of said address to form said selected logic functions, whereby changing said logic functions reconfigures the storage cells for a word location for converting uncorrectable double bit errors into correctable single bit errors.