Data storage apparatus

Claim 2

Data storage apparatus comprising: (a) a plurality of memory devices each having a plurality of individually addressable bit storage locations, the memory devices being arranged in a plurality of columns, (b) output means coupled to said memory devices, for reading out a bit from each said column to provide a multi-bit output data word, (c) error detecting means coupled to the output means for detecting n bit errors in said multi-bit output data word, where n is greater than one, and for generating an error signal upon detection of an arror, (d) a signal input path for inputting a control signal, and (e) a plurality of driver circuits each having an input connected to said input path to receive the control signal and an output connected to the memory devices in no more than n of said columns, at least some of the driver circuits having their outputs each connected to the memory devices in at least two of said columns, whereby, if any one of said driver circuits fails, no more than n bits in said output data word are corrupted and hence the failure can be detected by the error detecting means.

Claim 3

Apparatus according to claim 1 wherein at least some of the driver circuits have their outputs each connected to the memory devices in exactly n of said columns.

Claim 4

Data storage apparatus comprising: (a) a plurality of memory devices, each having a plurality of individually addressable bit storage locations, a data output, and an address input, the memory devices being arranged in a plurality of columns, (b) output means coupled to the data outputs of the memory devices, for reading out a bit from each said column to provide a multi-bit output data word, (c) error detecting means coupled to the output means for detecting n bit errors in said multi-bit output data word, where n is greater than one, and for generating an error signal upon detection of an error, (d) address input paths for inputting a multi-bit address signal, (e) a first plurality of driver circuits, each having an input connected to a respective one of the address input paths, and an output, (f) parity checking means connected to the outputs of the first plurality of driver circuits for checking the multi-bit address signal after it has passed through those driver circuits, and (g) for each of said first plurality of driver circuits, a further plurality of driver circuits, each having an input connected to the output of that first driver circuit and having an output connected to the address inputs of the memory devices in no more than n of said columns, at least some of the further plurality of driver circuits having their outputs each connected to the address inputs of the memory devices in at least two of said columns, whereby, if any one of said driver circuits fails, no more than n bits in said data output word are corrupted and hence the failure can be detected by the error detecting means.

Claim 5

Data storage apparatus comprising: (a) a plurality of memory devices, each having a plurality of individually addressable bit storage locations, a data output, and an address input, the memory devices being arranged in a plurality of columns, (b) output means coupled to the data outputs of the memory devices, for reading out a bit from each said column to provide a multi-bit output data word, (c) error detecting means coupled to the output means for detecting n bit errors in said multi-bit output data word, where n is greater than one, and for generating an error signal upon detection of an error, (d) address input paths for inputting a multi-bit address signal, (e) a first plurality of driver circuits, each having an input connected to a respective one of the address input paths, and an output, (f) parity checking means connected to the outputs of the first plurality of driver circuits for checking the multi-bit address signal after it has passed through those driver circuits, and (g) for each of said first plurality of driver circuits, a further plurality of driver circuits, each having an input connected to the output of that first driver circuit and having an output connected to the address inputs of the memory devices in no more than n of said columns, at least some of the further plurality of driver circuits having their outputs each connected to the address inputs of the memory devices in at least two of said columns, whereby, if any one of said driver circuits fails, no more than n bits in said data output word are corrupted and hence the failure can be detected by the error detecting means.