US4475194A
Expired / Lapsed
US
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Dynamic replacement of defective memory words
Assignee: International Business Machines Corp
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Filing: 1982-03-30
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Granted: 1984-10-02
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Expires: 2002-03-30
Abstract
Abstract A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply by providing a different address in the replacement page register.
Inventors
- 👤 Russell W. LaVallee
- 👤 Philip M. Ryan
- 👤 Vincent F. Sollitto, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:12
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
67 words
A memory system accessible in logical lines comprising: a memory; means for determining the presence of an uncorrectable error in a logical line accessed from said memory; means for dynamically deallocating an undedicated portion of said memory and on-line directing all future access from said logical line to said undedicated portion of said memory; and means for storing corrected data in said undedicated portion of said memory.
Claim 2
Dependent Claim
67 words
A memory system accessible in logical lines comprising: a memory; means for determining the presence of an uncorrectable error in a logical line accessed from said memory; means for dynamically deallocating an undedicated portion of said memory and on-line directing all future access from said logical line to said undedicated portion of said memory; and means for storing corrected data in said undedicated portion of said memory.
Claim 3
Dependent Claim
86 words
A memory system, accessible in logical lines for reading or writing data therein comprising: a memory; means for determining the presence of an uncorrectable error in a logical line of data read from said memory; means for dynamically deallocating an undedicated portion of said memory containing at least one logical line and for on-line substituting said logical line for said logical line containing an uncorrectable error whenever logical line containing an uncorrectable error is addressed; and means for storing corrected data in said substituted logical line.
Claim 4
Dependent Claim
86 words
A memory system, accessible in logical lines for reading or writing data therein comprising: a memory; means for determining the presence of an uncorrectable error in a logical line of data read from said memory; means for dynamically deallocating an undedicated portion of said memory containing at least one logical line and for on-line substituting said logical line for said logical line containing an uncorrectable error whenever logical line containing an uncorrectable error is addressed; and means for storing corrected data in said substituted logical line.
Claim 5
Independent Claim
41 words
The apparatus of claims 1 or 2 wherein said memory system comprises at least one basic storage module, a memory controller controlling the transfer of data between the basic storage module and the remainder of the system and a maintenance console.
Claim 6
Dependent Claim
22 words
The apparatus of claim 3 wherein said maintenance console includes error correcting code means for determining the presence of an uncorrectable error.
Claim 7
Dependent Claim
27 words
The apparatus claim 3 wherein said memory controller includes a line replacement array containing addresses of said logical line and said logical line containing an uncorrectable error.
Claim 8
Dependent Claim
29 words
The apparatus of claim 3 wherein said basic storage module includes a line replacement array containing addresses of said logical line and said logical line containing an uncorrectable error.
Claim 9
Independent Claim
100 words
A method of accessing a memory in logical lines some of which may contain uncorrectable errors comprising the steps of: fetching a logical line from said memory and determining the presence or lack thereof of an uncorrectable error; dynamically deallocating an undedicated portion of said memory if an uncorrectable error is determined; and comparing line addresses on future accesses to said memory to determine whether the logical line accessed is the line known to contain said uncorrectable error and if comparison results, on-line substituting the line address of said undedicated portion for the address of the line to be accessed.
Claim 10
Independent Claim
100 words
A method of accessing a memory in logical lines some of which may contain uncorrectable errors comprising the steps of: fetching a logical line from said memory and determining the presence or lack thereof of an uncorrectable error; dynamically deallocating an undedicated portion of said memory if an uncorrectable error is determined; and comparing line addresses on future accesses to said memory to determine whether the logical line accessed is the line known to contain said uncorrectable error and if comparison results, on-line substituting the line address of said undedicated portion for the address of the line to be accessed.
Claim 11
Dependent Claim
27 words
The method of claim 7 further comprising the steps of correcting any uncorrectable error data and storing corrected data at the line address in said undedicated portion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-02 | 1988-04-02 | 1988-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-02 | 1992-04-02 | 1992-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-02 | 1996-04-02 | 1996-10-02 | $7700.00 | Window Closed / Lapsed |